74HC273D

File under Integrated Circuits, IC06

September1993

Philips SemiconductorsProduct specification

Octal D-type flip-flop with reset;positive-edge trigger

FEATURES

•Ideal buffer for MOS microprocessor or memory•Common clock and master reset

•Eight positive edge-triggered D-type flip-flops•See “377” for clock enable version•See “373” for transparent latch version•See “374” for 3-state version•Output capability; standard•ICC category: MSI

GENERAL DESCRIPTION

74HC/HCT273

The 74HC/HCT273 are high-speed Si-gate CMOS devicesand are pin compatible with low power Schottky TTL(LSTTL). They are specified in compliance with JEDECstandard no. 7A.

The 74HC/HCT273 have eight edge-triggered, D-typeflip-flops with individual D inputs and Q outputs. The

common clock (CP) and master reset (MR) inputs load andreset (clear) all flip-flops simultaneously.

The state of each D input, one set-up time before theLOW-to-HIGH clock transition, is transferred to thecorresponding output (Qn) of the flip-flop.

All outputs will be forced LOW independently of clock ordata inputs by a LOW voltage level on theMR input.The device is useful for applications where the true outputonly is required and the clock and master reset arecommon to all storage elements.

QUICK REFERENCE DATA

GND=0 V; Tamb=25°C; tr=tf=6 nsSYMBOLtPHL/ tPLHPARAMETERpropagation delayCP to QnMR to QnfmaxCICPDNotes

1.CPD is used to determine the dynamic power dissipation (PD inµW):

PD=CPD× VCC2× fi+ ∑ (CL× VCC2 ×fo) where:fi=input frequency in MHzfo=output frequency in MHz∑ (CL× VCC2× fo)=sum of outputsCL=output load capacitance in pFVCC=supply voltage in V

2.For HC the condition is VI=GND to VCC

For HCT the condition is VI=GND to VCC− 1.5 VORDERING INFORMATION

See“74HC/HCT/HCU/HCMOS Logic Package Information”.

maximum clock frequencyinput capacitancepower dissipation capacitance per flip-flopnotes 1 and 2CONDITIONSCL=15 pF; VCC=5V1515663.5201520363.523nsnsMHzpFpFTYPICALHCHCTUNITSeptember19932

Philips SemiconductorsProduct specification

Octal D-type flip-flop with reset;positive-edge trigger

PIN DESCRIPTIONPIN NO.12, 5, 6, 9, 12, 15, 16, 193, 4, 7, 8, 13, 14, 17, 18101120SYMBOLMRQ0 to Q7D0 to D7GNDCPVCCNAME AND FUNCTIONmaster reset input (active LOW)flip-flop outputsdata inputsground (0 V)74HC/HCT273

clock input (LOW-to-HIGH, edge-triggered)positive supply voltageFig.1 Pin configuration.Fig.2 Logic symbol.Fig.3 IEC logic symbol.September19933

Philips SemiconductorsProduct specification

Octal D-type flip-flop with reset;positive-edge trigger

FUNCTION TABLEOPERATINGMODESreset (clear)load “1”load “0”Note

74HC/HCT273

INPUTSMRLHHCPX↑↑DnXhIOUTPUTSQnLHL1.H=HIGH voltage level

h=HIGH voltage level one set-up time prior to the

LOW-to-HIGH CP transitionL=LOW voltage level

I=LOW voltage level one set-up time prior to the

LOW-to-HIGH CP transition↑=LOW-to-HIGH transitionX=don’t care

Fig.4 Functional diagram.Fig.5 Logic diagram.September19934

Philips SemiconductorsProduct specification

Octal D-type flip-flop with reset;positive-edge trigger

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”.Output capability: standardICC category: MSI

AC CHARACTERISTICS FOR 74HCGND=0 V; tr=tf=6 ns; CL=50 pF

Tamb (°C)SYMBOLPARAMETERmin.tPHL/ tPLHpropagation delayCP to Qnpropagation delayMR to Qnoutput transition time74HC+25typ.411513441614197680161414541765−6−2−21143−6−2−220.6103122max.1503026150302675151310020177515136513117515133334.82428−40to+85min.max.1853731185373195191512024209018157515139018153334.02024−40to+125min.max.225453822545381102219ns74HC/HCT273

TEST CONDITIONSUNITVWAVEFORMSCC(V)2.04.56.02.04.56.02.04.56.02.04.56.02.04.56.02.04.56.02.04.56.02.04.56.02.04.56.0Fig.6tPHLnsFig.7tTHL/ tTLHnsFig.6tWclock pulse widthHIGH or LOWnsFig.6tWmaster reset pulse width60LOW1210removal timeMR to CPset-up timeDn to CPhold timeDn to CPmaximum clock pulsefrequency501096012103336.03035nsFig.7tremnsFig.7tsunsFig.8thnsFig.8fmaxMHzFig.6September19935

Philips SemiconductorsProduct specification

Octal D-type flip-flop with reset;positive-edge trigger

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”.Output capability: standardICC category: MSINote to HCT types

74HC/HCT273

The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.To determine∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUTMRCPDnUNIT LOAD COEFFICIENT1.001.750.15AC CHARACTERISTICS FOR 74HCTGND=0 V; tr=tf=6 ns; CL=50 pF

Tamb (°C)SYMBOLPARAMETERmin.tPHL/ tPLHtPHLtTHL/ tTLHtWtWtremtsuthfmaxpropagation delayCP to Qnpropagation delayMR to Qnoutput transition timeclock pulse widthHIGH or LOW1674HCT+25typ.1623798−25−456max.30341520201315324−40to+85min.max.38431924241518320TEST CONDITIONSUNITVWAVEFORMSCC−40to+125(V)min.max.455122nsnsnsnsnsnsnsnsMHz4.54.54.54.54.54.54.54.54.5Fig.6Fig.7Fig.6Fig.6Fig.7Fig.7Fig.8Fig.8Fig.6master reset pulse width16LOWremoval timeMR to CPset-up timeDn to CPhold timeDn to CPmaximum clock pulsefrequency1012330September19936

Philips SemiconductorsProduct specification

Octal D-type flip-flop with reset;positive-edge trigger

AC WAVEFORMS

74HC/HCT273

(1)HC: VM=50%; VI=GND to VCC.HCT: VM=1.3 V; VI=GND to 3 V.Fig.6Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width outputtransition times and the maximum clock pulse frequency.(1)HC: VM=50%; VI=GND to VCC.HCT: VM=1.3 V; VI=GND to 3 V.Fig.7Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delaysand the master reset to clock (CP) removal time.The shaded areas indicate when the input is permitted tochange for predictable output performance.(1)HC: VM=50%; VI=GND to VCC.HCT: VM=1.3 V; VI=GND to 3 V.Fig.8 Waveforms showing the data set-up and hold times for the data input (Dn).September19937

Philips SemiconductorsProduct specification

Octal D-type flip-flop with reset;positive-edge trigger

PACKAGE OUTLINES

See“74HC/HCT/HCU/HCMOS Logic Package Outlines”.

74HC/HCT273

September19938