Power MOS transistor for absorbing surge current

专利名称：Power MOS transistor for absorbing surge

current

发明人：Yasuhiro Kitamura,Toshio Sakakibara,Kenji

Kohno,Shoji Mizuno,Yoshiaki

Nakayama,Hiroshi Maeda,Makio Iida,HiroshiFujimoto,Mitsuhiro Saitou,HiroshiImai,Hiroyuki Ban

申请号：US09945621申请日：20010905公开号：US06831331B2公开日：20041214

专利附图：

摘要：A semiconductor device is provided having a power transistor structure. Thepower transistor structure includes a plurality of first wells disposed independently at asurface portion of a semiconductor layer; a deep region having a portion disposed in thesemiconductor layer between the first wells; a drain electrode connected to respectivedrain regions in the first wells; a source electrode connected to respective source regionsand channel well regions in the first wells, such that either the drain electrode or thesource electrode is connected to an inductive load; and a connecting member forsupplying the deep region with a source potential, where the connecting member isconfigurable to connect to the drain electrode when the drain electrode is connected tothe inductive load and to connect to the source electrode when the source electrode isconnected to said inductive load.

申请人：DENSO CORPORATION

代理机构：Harness, Dickey & Pierce, PLC

更多信息请下载全文后查看