Power MOS transistor having capability for setting

专利名称：Power MOS transistor having capability for

setting substrate potential independently ofsource potential

发明人：Takashi Nakano,Satoshi Shiraki,Yutaka

Fukuda,Nobumasa Ueda,Shoji Miura

申请号：US10160098申请日：20020604公开号：US07109558B2公开日：20060919

专利附图：

摘要：A power MOS transistor formed of an array of source cells and drain cells on an

IC chip substrate has a plurality of substrate contact cells, each formed external to thesource cells, having respective substrate potential-setting electrodes to which anexternally supplied substrate bias voltage can be applied, enabling the substratepotential to be set independently of the source potential of the transistor. It therebybecomes possible to modify the threshold voltage of the transistor or maintain aconstant potential difference between the substrate potential and that of a gate inputsignal. Since the requirement for a substrate contact region within each source cell iseliminated, and the number of substrate contact cells can be fewer than that of thesource cells, the chip area occupied by the transistor can be reduced by comparison witha prior art configuration providing such a substrate potential control capability.

申请人：Takashi Nakano,Satoshi Shiraki,Yutaka Fukuda,Nobumasa Ueda,Shoji Miura

地址：Aichi-ken JP,Toyohashi JP,Kariya JP,Nagoya JP,Aichi-ken JP

国籍：JP,JP,JP,JP,JP

代理机构：Posz Law Group, PLC

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