Pipeline module circuit structure with reduced pow

专利名称：Pipeline module circuit structure with

reduced power consumption and methodfor operating the same

发明人：Yung-Huei Chen,Hsiang-Chou Huang,Chih-Wei Hu

申请号：US10247471申请日：20020920

公开号：US20030131271A1公开日：20030710

专利附图：

摘要：A pipeline module circuit structure with reduced power consumption and a

method for operating the pipeline module circuit structure are provided. The pipelinemodule circuit structure comprises a plurality of pipeline stages and a clock generator,each of the pipeline stages connected to adjacent pipeline stages through a bus. A clockcontroller is installed in each of the pipeline stages, so as to set the clock frequency of apreceding pipeline stage to an idle frequency or stop when a present pipeline stagestarts to operate and to set the clock frequency of a next pipeline stage to an operationfrequency when the present pipeline stage is about to cease, such that the powerconsumption of the pipeline module circuit structure is effectively reduced.

申请人：CHEN YUNG-HUEI,HUANG HSIANG-CHOU,HU CHIH-WEI

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