SPRS377F–SEPTEMBER2008–REVISEDJUNE2014
6.8General-PurposeInput/Output(GPIO)
TheGPIOperipheralprovidesgeneral-purposepinsthatcanbeconfiguredaseitherinputsoroutputs.Whenconfiguredasanoutput,awritetoaninternalregistercancontrolthestatedrivenontheoutputpin.Whenconfiguredasaninput,thestateoftheinputisdetectablebyreadingthestateofaninternalregister.Inaddition,theGPIOperipheralcanproduceCPUinterruptsandEDMAeventsindifferentinterrupt/eventgenerationmodes.TheGPIOperipheralprovidesgenericconnectionstoexternaldevices.TheGPIOpinsaregroupedintobanksof16pinsperbank(i.e.,bank0consistsofGPIO[0:15]).
TheC6745/6747GPIOperipheralsupportsthefollowing:
•Upto128PinsonZKBandupto109PinsonPTPpackageconfigurableasGPIO•ExternalInterruptandDMArequestCapability
–EveryGPIOpinmaybeconfiguredtogenerateaninterruptrequestondetectionofrisingand/orfallingedgesonthepin.
–Theinterruptrequestswithineachbankarecombined(logicalor)tocreateeightuniquebanklevelinterruptrequests.
–ThebanklevelinterruptserviceroutinemaypolltheINTSTATxregisterforitsbanktodeterminewhichpin(s)havetriggeredtheinterrupt.
–GPIOBanks0,1,2,3,4,5,6,and7InterruptsassignedtoDSPEvents65,41,49,52,54,59,62and72respectively
–Additionally,GPIOBanks0,1,2,3,4,and5InterruptsassignedtoEDMAevents6,7,22,23,28,and29respectively.
•Set/clearfunctionality:Firmwarewrites1tocorrespondingbitposition(s)tosetortoclearGPIOsignal(s).ThisallowsmultiplefirmwareprocessestotoggleGPIOoutputsignalswithoutcriticalsectionprotection(disableinterrupts,programGPIO,re-enableinterrupts,topreventcontextswitchingtoantherprocessduringGPIOprogramming).•SeparateInput/Outputregisters
•Outputregisterinadditiontoset/clearsothat,ifpreferredbyfirmware,someGPIOoutputsignalscanbetoggledbydirectwritetotheoutputregister(s).
•Outputregister,whenread,reflectsoutputdrivestatus.This,inadditiontotheinputregisterreflectingpinstatusandopen-drainI/Ocell,allowswiredlogicbeimplemented.ThememorymapfortheGPIOregistersisshowninTable6-8.SeetheTMS320C6745/C6747DSPPeripheralsOverviewReferenceGuide.(SPRUFK9)formoredetails.
6.8.1GPIORegisterDescription(s)
Table6-8.GPIORegisters
BYTEADDRESS0x01E260000x01E260040x01E260080x01E260100x01E260140x01E260180x01E2601C0x01E260200x01E260240x01E260280x01E2602C0x01E26030
ACRONYM
REV-BINTENDIR01OUT_DATA01SET_DATA01CLR_DATA01IN_DATA01SET_RIS_TRIG01CLR_RIS_TRIG01SET_FAL_TRIG01CLR_FAL_TRIG01
GPIOBANKS0AND1
GPIOBanks0and1DirectionRegisterGPIOBanks0and1OutputDataRegisterGPIOBanks0and1SetDataRegisterGPIOBanks0and1ClearDataRegisterGPIOBanks0and1InputDataRegister
GPIOBanks0and1SetRisingEdgeInterruptRegisterGPIOBanks0and1ClearRisingEdgeInterruptRegisterGPIOBanks0and1SetFallingEdgeInterruptRegisterGPIOBanks0and1ClearFallingEdgeInterruptRegister
79
REGISTERDESCRIPTIONPeripheralRevisionRegister
Reserved
GPIOInterruptPer-BankEnableRegister
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SPRS377F–SEPTEMBER2008–REVISEDJUNE2014
Table6-8.GPIORegisters(continued)
BYTEADDRESS0x01E260340x01E260380x01E2603C0x01E260400x01E260440x01E260480x01E2604C0x01E260500x01E260540x01E260580x01E2605C0x01E260600x01E260640x01E260680x01E2606C0x01E260700x01E260740x01E260780x01E2607C0x01E260800x01E260840x01E260880x01E2608C0x01E260900x01E260940x01E260980x01E2609C0x01E260A00x01E260A40x01E260A80x01E260AC
ACRONYMINTSTAT01DIR23OUT_DATA23SET_DATA23CLR_DATA23IN_DATA23SET_RIS_TRIG23CLR_RIS_TRIG23SET_FAL_TRIG23CLR_FAL_TRIG23
INTSTAT23DIR45OUT_DATA45SET_DATA45CLR_DATA45IN_DATA45SET_RIS_TRIG45CLR_RIS_TRIG45SET_FAL_TRIG45CLR_FAL_TRIG45
INTSTAT45DIR67OUT_DATA67SET_DATA67CLR_DATA67IN_DATA67SET_RIS_TRIG67CLR_RIS_TRIG67SET_FAL_TRIG67CLR_FAL_TRIG67
INTSTAT67
GPIOBANKS2AND3
GPIOBanks2and3DirectionRegisterGPIOBanks2and3OutputDataRegisterGPIOBanks2and3SetDataRegisterGPIOBanks2and3ClearDataRegisterGPIOBanks2and3InputDataRegister
GPIOBanks2and3SetRisingEdgeInterruptRegisterGPIOBanks2and3ClearRisingEdgeInterruptRegisterGPIOBanks2and3SetFallingEdgeInterruptRegisterGPIOBanks2and3ClearFallingEdgeInterruptRegister
GPIOBanks2and3InterruptStatusRegister
GPIOBANKS4AND5
GPIOBanks4and5DirectionRegisterGPIOBanks4and5OutputDataRegisterGPIOBanks4and5SetDataRegisterGPIOBanks4and5ClearDataRegisterGPIOBanks4and5InputDataRegister
GPIOBanks4and5SetRisingEdgeInterruptRegisterGPIOBanks4and5ClearRisingEdgeInterruptRegisterGPIOBanks4and5SetFallingEdgeInterruptRegisterGPIOBanks4and5ClearFallingEdgeInterruptRegister
GPIOBanks4and5InterruptStatusRegister
GPIOBANKS6AND7
GPIOBanks6and7DirectionRegisterGPIOBanks6and7OutputDataRegisterGPIOBanks6and7SetDataRegisterGPIOBanks6and7ClearDataRegisterGPIOBanks6and7InputDataRegister
GPIOBanks6and7SetRisingEdgeInterruptRegisterGPIOBanks6and7ClearRisingEdgeInterruptRegisterGPIOBanks6and7SetFallingEdgeInterruptRegisterGPIOBanks6and7ClearFallingEdgeInterruptRegister
GPIOBanks6and7InterruptStatusRegister
REGISTERDESCRIPTION
GPIOBanks0and1InterruptStatusRegister
80
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