SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYSCAS338C – JANUARY 1994 – REVISED OCTOBER 1997DFree-Running CLKA and CLKB Can BeDDDDDDD Asynchronous or CoincidentClocked FIFO Buffering Data From Port Ato Port BMemory Size: 1024 ×36Synchronous Read-Retransmit CapabilityMailbox Register in Each DirectionProgrammable Almost-Full andAlmost-Empty FlagsMicroprocessor Interface Control LogicInput-Ready and Almost-Full FlagsSynchronized by CLKADOutput-Ready and Almost-Empty FlagsDDDDDSynchronized by CLKBLow-Power 0.8-µm Advanced CMOSTechnologySupports Clock Frequencies up to 67 MHzFast Access Times of 11 nsPin-to-Pin Compatible With theSN74ACT3631 and SN74ACT3651Package Options Include 120-Pin ThinQuad Flat (PCB) and 132-Pin Plastic QuadFlat (PQ) PackagesdescriptionThe SN74ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequenciesup to 67 MHz and has read access times as fast as 12 ns. The 1024 × 36 dual-port SRAM FIFO buffers datafrom port A to port B. The FIFO memory has retransmit capability, which allows previously read data to beaccessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almostfull and almost empty) to indicate when a selected number of words is stored in memory. Communicationbetween each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag to signal whennew mail has been stored. Two or more devices are used in parallel to create wider datapaths. Expansion isalso possible in word depth.The SN74ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All datatransfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enablesignals. The continuous clocks for each port are independent of one another and can be asynchronous orcoincident. The enables for each port are arranged to provide a simple interface between microprocessorsand/or buses with synchronous control.The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to CLKA. Theoutput-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offsetvalues for the AF and AE flags of the FIFO can be programmed from port A or through a serial input.The SN74ACT3641 is characterized for operation from 0°C to 70°C.For more information on this device family, see the following application reports:•••FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering(literature number SCAA009)FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007)Metastability Performance of Clocked FIFOs (literature number SCZA004)Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 1997, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYPCB PACKAGE(TOP VIEW) NC – No internal connection2GNDA11A10A9A8A7A6GNDA5A4A3VCCA2A1A0GNDB0B1B2B3B4B5GNDB6VCCPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•B7B8B9B10B11313233343536373839404142434445464748495051525354555657585960A35A34A33A32VCCA31A30GNDA29A28A27A26A25A24A23GNDA22VCCA21A20A19A18GNDA17A16A15A14A13VCCA12120119118117116115114113112111110109108107106105104103102101100 99 98 97 96 95 94 93 92 91GNDCLKAENAW/RACSAIRORVCCAFAEVCCMBF2MBARSTGNDFS0/SDFS1/SENRTMRFMVCCNCMBBGNDMBF1GNDCSBW/RBENBCLKBVCC123456789101112131415161718192021222324252627282930908988878685848382818079787776757473727170696867666564636261B35B34B33B32GNDB31B30B29B28B27B26VCCB25B24GNDB23B22B21B20B19B18GNDB17B16VCCB15B14B13B12GND SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYSCAS338C – JANUARY 1994 – REVISED OCTOBER 1997PQ PACKAGE†(TOP VIEW)NCB35B34B33B32GNDB31B30B29B28B27B26VCCB25B24GNDB23B22B21B20B19B18GNDB17B16VCCB15B14B13B12GNDNCNCNCNCVCCCLKBENBW/RBCSBGNDMBF1GNDMBBNCVCCRFMRTMFS1/SENFS0/SDGNDRSTMBAMBF2VCCAEAFVCCORIRCSAW/RAENACLKAGNDNC171615141312111091819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838765432113213012812612412212011812912111913112712512311711611511411311211111010910810710610510410310210110099989796959493929190898887868584NCNCA35A34A33A32VCCA31A30GNDA29A28A27A26A25A24A23GNDA22VCCA21A20A19A18GNDA17A16A15A14A13VCCA12NCNC – No internal connection†Uses Yamaichi socket IC51-1324-828NCB11B10B9B8B7VCCB6GNDB5B4B3B2B1B0GNDA0A1A2VCCA3A4A5GNDA6A7A8A9A10A11GNDNCNCPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•3SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYfunctional block diagramMBF1Mail1RegisterPort-AControlLogic 1024× 36SRAMRSTResetLogicSynchRetransmitLogicOutput RegisterInput RegisterCLKACSAW/RAENAMBA36RTMRFMWritePointerA0–A35IRAFReadPointerB0–B35Status-FlagLogicORAEFS0/SDFS1/SEN10Flag-OffsetRegisterMail2RegisterMBF2Port-BControlLogicCLKBCSBW/RBENBMBB4POST OFFICE BOX 655303 DALLAS, TEXAS 75265• SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYSCAS338C – JANUARY 1994 – REVISED OCTOBER 1997Terminal FunctionsTERMINAL NAMEA0–A35AEAFB0–B35CLKACLKBCSACSBENAENBI/OI/OOOI/OIIIIIIDESCRIPTIONPort-A data. The 36-bit bidirectional data port for side A.Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is lessthan or equal to the value in the almost-empty offset register (X).Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFOis less than or equal to the value in the almost-full offset register (Y).Port-B data. The 36-bit bidirectional data port for side B.Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronousor coincident to CLKB. IR and AF are synchronous to the low-to-high transition of CLKA.Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronousor coincident to CLKA. OR and AE are synchronous to the low-to-high transition of CLKB.Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. TheA0–A35 outputs are in the high-impedance state when CSA is high.Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. TheB0–B35 outputs are in the high-impedance state when CSB is high.Port-A master enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.Port-B master enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.Flag-offset select 1/serial enable, flag-offset select 0/serial data. FS1/SEN and FS0/SD are dual-purpose inputs usedfor flag-offset register programming. During a device reset, FS1/SEN and FS0/SD select the flag-offset programmingmethod. Three offset-register programming methods are available: automatically load one of two preset values, parallelload from port A, and serial load.When serial load is selected for flag-offset-register programming, FS1/SEN is used as an enable synchronous to thelow-to-high transition of CLKA. When FS1/SEN is low, a rising edge on CLKA loads the bit present on FS0/SD into theX-and Y-offset registers. The number of bit writes required to program the offset registers is 20. The first bit write storesthe Y-register MSB and the last bit write stores the X-register LSB.Input-ready flag. IR is synchronized to the low-to-high transition of CLKA. When IR is low, the FIFO is full and writes toits array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the pointof the retransmit data and prevents further writes. IR is set low during reset and is set high after reset.Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When theB0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selectsFIFO data for output.Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. MBF1is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high by areset.Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. MBF2is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high by areset.Output-ready flag. OR is synchronized to the low-to-high transition of CLKB. When OR is low, the FIFO is empty andreads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low duringthe reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory.Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB to resetthe read pointer to the beginning retransmit location and output the first selected retransmit data.Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occurwhile RST is low. The low-to-high transition of RST latches the status of FS0 and FS1 for AF and AE offset selection.Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR is high), a low-to-hightransition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selectedword remains the initial retransmit point until a low-to-high transition of CLKB occurs while RTM is low, taking the FIFOout of retransmit mode.FS1/SEN,FS0/SDIIRMBAMBBOIIMBF1OMBF2OORORFMRSTIIRTMIPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYTerminal Functions (Continued)TERMINALNAMEW/RAW/RBI/OIIDESCRIPTIONPort-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for alow-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/RA is high.Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for alow-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/RB is low. detailed descriptionresetThe SN74ACT3641 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and fourport-B clock (CLKB) low-to-high transitions. RST can switch asynchronously to the clocks. A reset initializes thememory read and write pointers and forces the IR flag low, the OR flag low, the AE flag low, and the AF flag high.Resetting the device also forces the mailbox flags (MBF1, MBF2) high. After a FIFO is reset, its flag is set highafter at least two clock cycles to begin normal operation. A FIFO must be reset after power up before data iswritten to its memory.almost-empty flag and almost-full flag offset programmingTwo registers in the SN74ACT3641 are used to hold the offset values for the AE and AF flags. The AE flag offsetregister is labeled X, and the AF flag offset register is labeled Y. The offset registers can be loaded with a valuein three ways: one of two preset values are loaded into the offset registers, parallel load from port A, or serialload. The offset register programming mode is chosen by the flag select (FS1, FS0) inputs during a low-to-hightransition on RST (see Table 1).Table 1. Flag ProgrammingFS1HHLLFS0HLHLRST↑↑↑↑X AND Y REGISTERS†Serial load648Parallel load from port A†X register holds the offset for AE; Y register holds theoffset for AF.preset valuesIf a preset value of 8 or 64 is chosen by FS1 and FS0 at the time of a RST low-to-high transition according toTable 1, the preset value is automatically loaded into the X and Y registers. No other device initialization isnecessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on CLKA.parallel load from port ATo program the X and Y registers from port A, the device is reset with FS0 and FS1 low during the low-to-hightransition of RST. After this reset is complete, IR is set high after two low-to-high transitions on CLKA. The firsttwo writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X. Each offsetregister of the SN74ACT3641 uses port-A inputs (A9–A0). Data input A9 is used as the most-significant bit ofthe binary number. Each register value can be programmed from 1 to 1020. After both offset registers areprogrammed from port A, subsequent FIFO writes store data in the SRAM.6POST OFFICE BOX 655303 DALLAS, TEXAS 75265• SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYSCAS338C – JANUARY 1994 – REVISED OCTOBER 1997serial loadTo program the X and Y registers serially, the device is reset with FS0/SD and FS1/SEN high during thelow-to-high transition of RST. After this reset is complete, the X-and Y-register values are loaded bitwise throughFS0/SD on each low-to-high transition of CLKA that FS1/SEN is low. Twenty bit writes are needed to completethe programming. The first bit write stores the most-significant bit of the Y register and the last bit write storesthe least-significant bit of the the X register. Each register value can be programmed from 1 to 1020.When the option to program the offset registers serially is chosen, the IR remains low until all 20 bits are written.IR is set high by the low-to-high transition of CLKA after the last bit is loaded to allow normal FIFO operation.FIFO write/read operationThe state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA) and the port-Awrite/read select (W/RA). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA ishigh. The A0–A35 outputs are active when both CSA and W/RA are low.Data is loaded into the FIFO from the A0–A35 inputs on a low-to-high transition of CLKA when CSA and theport-A mailbox select (MBA) are low, W/RA, the port-A enable (ENA), and the IR flag are high (see Table 2).Writes to the FIFO are independent of any concurrent FIFO reads.Table 2. Port-A Enable Function TableCSAHLLLLLLLW/RAXHHHLLLLENAXLHHLHLHMBAXXLHLLHHCLKAXX↑↑X↑X↑A0–A35 OUTPUTSIn high-impedance stateIn high-impedance stateIn high-impedance stateIn high-impedance stateActive, mail2 registerActive, mail2 registerActive, mail2 registerActive, mail2 registerPORT FUNCTIONNoneNoneFIFO writeMail1 writeNoneNoneNoneMail2 read (set MBF2 high)The port-B control signals are identical to those of port A, with the exception that the port-B write/read select(W/RB) is the inverse of W/RA. The state of the port-B data (B0–B35) outputs is controlled by the port-B chipselect (CSB) and W/RB. The B0–B35 outputs are in the high-impedance state when either CSB is high or W/RBis low. The B0–B35 outputs are active when CSB is low and W/RB is high.Data is read from the FIFO to its output register on a low-to-high transition of CLKB when CSB and the port-Bmailbox select (MBB) are low, W/RB, the port-B enable (ENB), and the OR flag are high (see Table 3). Readsfrom the FIFO are independent of any concurrent FIFO writes.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•7SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYFIFO write/read operation (continued)Table 3. Port-B Enable Function TableCSBHLLLLLLLW/RBXLLLHHHHENBXLHHLHLHMBBXXLHLLHHCLKBXX↑↑X↑X↑B0–B35 OUTPUTSIn high-impedance stateIn high-impedance stateIn high-impedance stateIn high-impedance stateActive, FIFO output registerActive, FIFO output registerActive, mail1 registerActive, mail1 registerPORT FUNCTIONNoneNoneNoneMail2 writeNoneFIFO readNoneMail1 read (set MBF1 high) The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are onlyfor enabling write and read operations and are not related to high-impedance control of the data outputs. If aport enable is low during a clock cycle, the port-chip select and write/read select can change states during thesetup- and hold-time window of the cycle.When the OR is low, the next data word is sent to the FIFO output register automatically by the CLKB low-to-hightransition that sets OR high. When OR is high, an available data word is clocked to the FIFO output register onlywhen a FIFO read is selected by CSB, W/RB, ENB, and MBB.synchronized FIFO flagsEach FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve theflag’s reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operateasynchronously to one another. OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA.Table 4 shows the relationship of each flag to the number of words stored in memory.Table 4. FIFO Flag OperationNUMBER OF WORDS INFIFO†‡01 to X(X + 1) to [1024 – (Y + 1)](1024 – Y) to 10231024SYNCHRONIZEDTO CLKBORLHHHHAELLHHHSYNCHRONIZEDTO CLKAAFHHHLLIRHHHHL†X is the almost-empty offset for AE. Y is the almost-full offset for AF.‡When a word is present in the FIFO output register, its previous memorylocation is free.8POST OFFICE BOX 655303 DALLAS, TEXAS 75265• SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYSCAS338C – JANUARY 1994 – REVISED OCTOBER 1997output-ready flag (OR)The OR flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). When the ORflag is high, new data is present in the FIFO output register. When the OR flag is low, the previous data wordis present in the FIFO output register and attempted FIFO reads are ignored.A FIFO read pointer is incremented each time a new word is clocked to its output register. From the time a wordis written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of CLKB; therefore,an OR flag is low if a word in memory is the next data to be sent to the FIFO output register and three CLKBcycles have not elapsed since the time the word was written. The OR flag of the FIFO remains low until the thirdlow-to-high transition of CLKB occurs, simultaneously forcing the OR flag high and shifting the word to the FIFOoutput register.A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transitionoccurs at time tsk(1), or greater, after the write. Otherwise, the subsequent CLKB cycle can be the firstsynchronization cycle (see Figure 6).input-ready flag (IR)The IR flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). When the IR flag ishigh, a memory location is free in the SRAM to write new data. No memory locations are free when the IR flagis low and attempted writes to the FIFO are ignored.Each time a word is written to a FIFO, its write pointer is incremented. From the time a word is read from a FIFO,its previous memory location is ready to be written in a minimum of three cycles of CLKA; therefore, an IR flagis low if less than two cycles of CLKA have elapsed since the next memory write location has been read. Thesecond low-to-high transition on CLKA after the read sets the IR flag high, and data can be written in the followingcycle.A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transitionoccurs at time tsk(1), or greater, after the read. Otherwise, the subsequent CLKA cycle can be the firstsynchronization cycle (see Figure 7).almost-empty flag (AE)The AE flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). The almost-emptystate is defined by the contents of register X. This register is loaded with a preset value during a FIFO reset,programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offsetprogramming). The AE flag is low when the FIFO contains X or fewer words and is high when the FIFO contains(X + 1) or more words. A data word present in the FIFO output register has been read from memory.Two low-to-high transitions of CLKB are required after a FIFO write for the AE flag to reflect the new level offill; therefore, the AE flag of a FIFO containing (X + 1) or more words remains low if two cycles of CLKB havenot elapsed since the write that filled the memory to the (X + 1) level. An AE flag is set high by the secondlow-to-high transition of CLKB after the FIFO write that fills memory to the (X + 1) level.A low-to-high transition of CLKB begins the first synchronization cycle if it occurs at time tsk(2), or greater, afterthe write that fills the FIFO to (X + 1) words. Otherwise, the subsequent CLKB cycle can be the firstsynchronization cycle (see Figure 8).POST OFFICE BOX 655303 DALLAS, TEXAS 75265•9SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYalmost-full flag (AF) The AF flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). The almost-full stateis defined by the contents of register Y. This register is loaded with a preset value during a FIFO reset,programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offsetprogramming). The AF flag is low when the number of words in the FIFO is greater than or equal to (1024 – Y).The AF flag is high when the number of words in the FIFO is less than or equal to [1024 – (Y + 1)]. A data wordpresent in the FIFO output register has been read from memory.Two low-to-high transitions of CLKA are required after a FIFO read for its AF flag to reflect the new level of fill.Therefore, the AF flag of a FIFO containing [1024 – (Y + 1)] or fewer words remains low if two cycles of CLKAhave not elapsed since the read that reduced the number of words in memory to [1024 – (Y + 1)]. An AF flagis set high by the second low-to-high transition of CLKA after the FIFO read that reduces the number of wordsin memory to [1024 – (Y + 1)]. A low-to-high transition of CLKA begins the first synchronization cycle if it occursat time tsk(2), or greater, after the read that reduces the number of words in memory to [1024 – (Y + 1)].Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 9).synchronous retransmitThe synchronous retransmit feature of the SN74ACT3641 allows FIFO data to be read repeatedly starting ata user-selected position. The FIFO is first put into retransmit mode to select a beginning word and preventongoing FIFO write operations from destroying retransmit data. Data vectors with a minimum length of threewords can retransmit repeatedly, starting at the selected word. The FIFO can be taken out of retransmit modeat any time and allow normal device operation.The FIFO is put in retransmit mode by a low-to-high transition on CLKB when the retransmit mode (RTM) inputis high and OR is high. This rising CLKB edge marks the data present in the FIFO output register as the firstretransmit data. The FIFO remains in retransmit mode until a low-to-high transition occurs while RTM is low.When two or more reads have been done past the initial retransmit word, a retransmit is initiated by a low-to-hightransition on CLKB when the read-from-mark (RFM) input is high. This rising CLKB edge shifts the firstretransmit word to the FIFO output register and subsequent reads can begin immediately. Retransmit loops canbe done endlessly while the FIFO is in retransmit mode. RFM must be low during the CLKB rising edge that takesthe FIFO out of retransmit mode.When the FIFO is put into retransmit mode, it operates with two read pointers. The current read pointer operatesnormally, incrementing each time a new word is shifted to the FIFO output register and used by the OR and AEflags. The shadow read pointer stores the SRAM location at the time the device is put into retransmit mode anddoes not change until the device is taken out of retransmit mode. The shadow read pointer is used by the IRand AF flags. Data writes can proceed while the FIFO is in retransmit mode, but AF is set low by the write thatstores (1024 – Y) words after the first retransmit word. The IR flag is set low by the 1024th write after the firstretransmit word.When the FIFO is in retransmit mode and RFM is high, a rising CLKB edge loads the current read pointer withthe shadow read-pointer value and the OR flag reflects the new level of fill immediately. If the retransmit changesthe FIFO status out of the almost-empty range, up to two CLKB rising edges after the retransmit cycle areneeded to switch AE high (see Figure 11). The rising CLKB edge that takes the FIFO out of retransmit modeshifts the read pointer used by the IR and AF flags from the shadow to the current read pointer. If the changeof read pointer used by IR and AF should cause one or both flags to transition high, at least two CLKAsynchronizing cycles are needed before the flags reflect the change. A rising CLKA edge after the FIFO is takenout of retransmit mode is the first synchronizing cycle of IR if it occurs at time tsk(1), or greater, after the risingCLKB edge (see Figure 12). A rising CLKA edge after the FIFO is taken out of retransmit mode is the firstsynchronizing cycle of AF if it occurs at time tsk(2), or greater, after the rising CLKB edge (see Figure 14).10POST OFFICE BOX 655303 DALLAS, TEXAS 75265• SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYSCAS338C – JANUARY 1994 – REVISED OCTOBER 1997mailbox registersTwo 36-bit bypass registers are on the SN74ACT3641 to pass command and control information between port Aand port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port datatransfer operation. A low-to-high transition on CLKA writes A0–A35 data to the mail1 register when a port A writeis selected by CSA, W/RA, and ENA with MBA high. A low-to-high transition on CLKB writes B0–B35 data tothe mail2 register when a port-B write is selected by CSB, W/RB, and ENB with MBB high. Writing data to a mailregister sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored whileits mail flag is low.When the port-B data (B0–B35) outputs are active, the data on the bus comes from the FIFO output registerwhen the port-B mailbox select (MBB) input is low and from the mail1 register when MBB is high. Mail2 datais always present on the port-A data (A0–A35) outputs when they are active. The mail1 register flag (MBF1)is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB withMBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A readis selected by CSA, W/RA, and ENA with MBA high. The data in a mail register remains intact after it is readand changes only when new data is written to the register.CLKACLKBtsu(RS)RSTFS1, FS00,1tsu(FS)th(RS)th(FS)tpd(C-IR)IRtpd(C-IR)tpd(C-OR)ORtpd(R-F)AEtpd(R-F)AFMBF1,MBF2tpd(R-F)Figure 1. FIFO Reset Loading X and Y With a Preset Value of EightPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•11SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYCLKARSTtsu(FS)FS1, FS0tpd(C-IR)IRtsu(EN1)ENA 4th(FS)th(EN1)tsu(D)A0–A35th(D)AF Offset(Y)AE Offset(X)First Word Stored in FIFONOTE A:CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.Figure 2. Programming the AF Flag and AE Flag Offset Values From Port ACLKARST4tpd(C-IR)IRtsu(FS)FS1/SENth(SP)tsu(SEN)th(SEN)tsu(SEN)th(SEN)tsu(FS)FS0/SDth(SD)th(FS)tsu(SD)tsu(SD)AE Offset(X) LSBth(SD)AF Offset(Y) MSBNOTE A:It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set high.Figure 3. Programming the AF Flag and AE Flag Offset Values Serially12POST OFFICE BOX 655303 DALLAS, TEXAS 75265• SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYSCAS338C – JANUARY 1994 – REVISED OCTOBER 1997tctw(CLKH)CLKAtw(CLKL)IRHightsu(EN2)th(EN2)CSAtsu(EN2)W/RAth(EN2)tsu(EN2)MBAth(EN2)tsu(EN1)ENAtsu(D)A0–A35W1th(EN1)tsu(EN1)th(D)W2th(EN1)tsu(EN1)th(EN1)No OperationFigure 4. FIFO Write-Cycle Timingtctw(CLKH)CLKBtw(CLKL)ORCSBHighW/RBMBBtsu(EN1)th(EN1)ENBtsu(EN1)th(EN1)tsu(EN1)th(EN1)tpd(M-DV)tenB0–B35taW1W2taNoOperationW3tdisFigure 5. FIFO Read-Cycle TimingPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•13SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYtctw(CLKH)CLKALowHightsu(EN2)tsu(EN1)ENAIRA0–A35tw(CLKL) CSAW/RAMBAth(EN2)th(EN1)Hightsu(D)th(D)tctw(CLKL)1Old Data in FIFO Output Register2tpd(C-OR)3tpd(C-OR)W1tsk(1)†tw(CLKH)CLKBORCSBW/RBMBBENBLowHighLowtsu(EN1)taB0–B35Old Data in FIFO Output Registerth(EN1)W1†tsk(1) is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition high and to clock the next word to theFIFO output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tsk(1), the transitionof OR high and the first word load to the output register can occur one CLKB cycle later than shown.Figure 6. OR-Flag Timing and First Data-Word Fall-Through When the FIFO Is Empty14POST OFFICE BOX 655303 DALLAS, TEXAS 75265• SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYSCAS338C – JANUARY 1994 – REVISED OCTOBER 1997tctw(CLKH)CLKBCSBW/RBMBBENBORLowHighLowtsu(EN1)tw(CLKL)th(EN1)HightaB0–B35FIFO Output Registertsk(1)†tw(CLKH)Next Word From FIFOtc1tw(CLKL)2tpd(C-IR)tpd(C-IR)CLKAIRCSAW/RAMBALowHighFIFO Fulltsu(EN2)tsu(EN1)th(EN2)th(EN1)ENAA0–A35tsu(D)th(D)Write†tsk(1) is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the timebetween the rising CLKB edge and rising CLKA edge is less than tsk(1), IR can transition high one CLKA cycle later than shown.Figure 7. IR-Flag Timing and First Available Write When the FIFO Is FullPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•15SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYCLKAtsu(EN1)ENAtsk(2)†CLKBAEENBX Words in FIFO1tpd(C-AE)2tpd(C-AE)(X + 1) Words in FIFOtsu(EN1)th(EN1)th(EN1) †tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition high in the next CLKB cycle. If the timebetween the rising CLKA edge and rising CLKB edge is less than tsk(2), AE can transition high one CLKB cycle later than shown.NOTE A:FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)Figure 8. Timing for AE When FIFO Is Almost Emptytsk(2)‡CLKAtsu(EN1)ENAtpd(C-AF)AF[1024 – (Y + 1)] Words in FIFO(1024 – Y) Words in FIFOth(EN1)12tpd(C-AF)CLKBtsu(EN1)ENBth(EN1)‡tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition high in the next CLKA cycle. If the timebetween the rising CLKB edge and rising CLKA edge is less than tsk(2), AF can transition high one CLKA cycle later than shown.NOTE A:FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)Figure 9. Timing for AF When FIFO Is Almost Full16POST OFFICE BOX 655303 DALLAS, TEXAS 75265• SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYSCAS338C – JANUARY 1994 – REVISED OCTOBER 1997CLKBtsu(EN1)ENBtsu(RM)RTMtsu(RM)RFMth(RM)th(RM)tsu(RM)th(RM)th(EN1)ORHightataW1W2Retransmit FromSelected PositiontaW0End RetransmitModetaW1B0–B35W0Initiate Retransmit ModeWith W0 as First WordNOTE A:CSB = L, W/RB = H, MBB = L. No input enables other than RTM and RFM are needed to control retransmit mode or begin aretransmit. Other enables are shown only to relate retransmit operations to the FIFO output register.Figure 10. Retransmit Timing Showing Minimum Retransmit LengthCLKB12RTMHightsu(RM)th(RM)RFMtpd(C-AE)AEX or Fewer Words From Empty(X + 1) or More Words From EmptyNOTE A:X is the value loaded in the AE flag offset register.Figure 11. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above XPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•17SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYtsk(1)†CLKA1tpd(C-IR)IRFIFO Filled to First Retransmit WordOne or More Write Locations Available2 CLKBtsu(RM)RTMth(RM)†tsk(1) is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the timebetween the rising CLKB edge and rising CLKA edge is less than tsk(1), IR can transition high one CLKA cycle later than shown.Figure 12. IR Timing From the End of Retransmit Mode When One or More Write Locations Are Availabletsk(2)‡CLKA1tpd(C-AE)AF(1024 – Y) or More Words Past First Retransmit Word(Y + 1) or More Write Locations Available2CLKBtsu(RM)RTMth(RM)‡tsk(2) is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition high in the next CLKA cycle. If the timebetween the rising CLKB edge and rising CLKA edge is less than tsk(2), AF can transition high one CLKA cycle later than shown.NOTE A:Y is the value loaded in the AF flag offset register.Figure 13. AF Timing From the End of Retransmit Mode When (Y + 1)or More Write Locations Are Available18POST OFFICE BOX 655303 DALLAS, TEXAS 75265• SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYSCAS338C – JANUARY 1994 – REVISED OCTOBER 1997CLKAtsu(EN2)CSAth(EN2)W/RAMBAENAtsu(D)A0–A35th(D)W1CLKBtpd(C-MF)MBF1CSBW/RBMBBtsu(EN1)ENBtenB0–B35FIFO Output Registertpd(M-DV)tpd(C-MR)tdistpd(C-MF)th(EN1)W1 (remains valid in mail1 register after read)Figure 14. Timing for Mail1 Register and MBF1 FlagPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•19SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYCLKBtsu(EN2)CSBth(EN2) W/RBMBBENBtsu(D)B0–B35th(D)W1CLKAtpd(C-MF)MBF2CSAW/RAMBAENAtenA0–A35tpd(C-MR)tpd(C-MF)tsu(EN1)th(EN1)tdisW1 (remains valid in mail2 register after read)Figure 15. Timing for Mail2 Register and MBF2 Flag20POST OFFICE BOX 655303 DALLAS, TEXAS 75265• SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYSCAS338C – JANUARY 1994 – REVISED OCTOBER 1997absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 VInput voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 VOutput voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 VInput clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAOutput clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAContinuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAContinuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mAPackage thermal impedance, θJA (see Note 2):PCB package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/WPQ package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CStorage temperature range, Tstg –65†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.2.The package thermal impedance is calculated in accordance with JESD 51.recommended operating conditionsMINVCCVIHVILIOHIOLTASupply voltageHigh-level input voltageLow-level input voltageHigh-level output currentLow-level output currentOperating free-air temperature04.520.8–4870MAX5.5UNITVVVmAmA°Celectrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERVOHVOLIIIOZICCVCC = 4.5 V,VCC = 4.5 V,VCC = 5.5 V,VCC = 5.5 V,VCC = 5.5 V,TEST CONDITIONSIOH = –4 mAIOL = 8 mAVI = VCC or 0VO = VCC or 0VI = VCC – 0.2 V or 0CSA = VIH∆ICC§VCC = 5.5 V, One input at 3.4 V,55VOitt34VOther inuts at VOtherinputsatVCC or GNDorGNDCSB = VIHCSA = VILCSB = VILAll other inputsCiCoVI = 0,VO = 0,f = 1 MHzf = 1 MHz48A0–A35B0–B35A0–A35B0–B3500111pFpFmAMIN2.40.5±5±5400TYP‡MAXUNITVVµAµAµA‡All typical values are at VCC = 5 V, TA = 25°C.§This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•21SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORY timing requirements over recommended ranges of supply voltage and operating free-airtemperature (see Figures 1 through 16)’ACT3641-15MINfclocktctw(CH)tw(CL)tsu(D)tsu(EN1)tsu(EN2)tsu(RM)tsu(RS)tsu(FS)tsu(SD)‡tsu(SEN)‡th(D)tn(EN1)tn(EN2)tn(RM)th(RS)th(FS)th(SP)‡th(SD)‡th(SEN)‡tsk(1)§Clock frequency, CLKA or CLKBClock cycle time, CLKA or CLKBPulse duration, CLKA and CLKB highPulse duration, CLKA and CLKB lowSetup time, A0–A35 before CLKA↑and B0–B35 before CLKB↑Setup time, ENA to CLKA↑; ENB to CLKB↑Setup time, CSA, W/RA, and MBA to CLKA↑; CSB, W/RB, and MBB to CLKB↑Setup time, RTM and RFM to CLKB↑Setup time, RST low before CLKA↑ or CLKB↑†Setup time, FS0 and FS1 before RST highSetup time, FS0/SD before CLKA↑Setup time, FS1/SEN before CLKA↑Hold time, A0–A35 after CLKA↑and B0–B35 after CLKB↑Hold time, ENA after CLKA↑; ENB after CLKB↑Hold time, CSA, W/RA, and MBA after CLKA↑;CSB, W/RB, and MBB after CLKB↑Hold time, RTM and RFM after CLKB↑Hold time, RST low after CLKA↑ or CLKB↑†Hold time, FS0 and FS1 after RST highHold time, FS1/SEN high after RST highHold time, FS0/SD after CLKA↑Hold time, FS1/SEN after CLKA↑Skew time between CLKA↑ and CLKB↑ for OR and IR1566557659550000500009MAX66.72088667.56.56106600006000011’ACT3641-20MINMAX5030121277877117700007000013’ACT3641-30MINMAX33.4UNITMHznsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnstsk(2)§Skew time between CLKA↑ and CLKB↑ for AE and AF121620ns†Requirement to count the clock edge as one of at least four needed to reset a FIFO‡Applies only when serial load method is used to program flag-offset registers§Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle andCLKB cycle.22POST OFFICE BOX 655303 DALLAS, TEXAS 75265• SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYSCAS338C – JANUARY 1994 – REVISED OCTOBER 1997switching characteristics over recommended ranges of supply voltage and operating free-airtemperature, CL = 30 pF (see Figures 1 through 15)PARAMETERfmaxtatpd(C-IR)tpd(C-OR)tpd(C-AE)tpd(C-AF)tpd(C-MF)tpd(C-MR)tpd(M-DV)tpd(R-F)tentdis’ACT3641-15MIN66.7Access time, CLKB↑ to B0–B35Propagation delay time, CLKA↑ to IRPropagation delay time, CLKB↑ to ORPropagation delay time, CLKB↑ to AEPropagation delay time, CLKA↑ to AFPropagation delay time, CLKA↑ to MBF1 low or MBF2 high andCLKB↑ to MBF2 low or MBF1 highPropagation delay time, CLKA↑ to B0–B35† and CLKB↑ toA0–A35‡Propagation delay time, MBB to B0–B35 validPropagation delay time, RST low to AE low and AF highEnable time, CSA and W/RA low to A0–A35 active and CSB lowand W/RB high to B0–B35 activeDisable time, CSA or W/RA high to A0–A35 at high impedanceand CSB high or W/RB low to B0–B35 at high impedance31111033121118888813.51315128MAX’ACT3641-20MIN50311110331211310101010101515201310MAX’ACT3641-30MIN33.4311110331211512121212121717301411MAXUNITMHznsnsnsnsnsnsnsnsnsnsns†Writing data to the mail1 register when the B0–B35 outputs are active and MBB is high‡Writing data to the mail2 register when the A0–A35 outputs are active and MBA is highPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•23SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYPARAMETER MEASUREMENT INFORMATION5 V 1.1 kΩFrom OutputUnder Test680 Ω30 pF(see Note A)LOAD CIRCUITTimingInputtsuData,EnableInput1.5 V3 V1.5 VGNDth3 V1.5 VGNDVOLTAGE WAVEFORMSSETUP AND HOLD TIMES3 V1.5 VtPLZ1.5 VGNDtPZL1.5 VtPZHVOLVOH1.5 V≈ 0 VtPHZVOLTAGE WAVEFORMSENABLE AND DISABLE TIMES≈ 3 VHigh-LevelInput3 V1.5 Vtw1.5 VGNDLow-LevelInput3 V1.5 V1.5 VGNDVOLTAGE WAVEFORMSPULSE DURATIONSOutputEnableLow-LevelOutput3 VInputtpdIn-PhaseOutput1.5 V1.5 V1.5 VGNDtpdVOH1.5 VVOLVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESHigh-LevelOutputNOTES:A.Includes probe and jig capacitanceB.tPZL and tPZH are the same as tenC.tPLZ and tPHZ are the same as tdisFigure 16. Load Circuit and Voltage Waveforms24POST OFFICE BOX 655303 DALLAS, TEXAS 75265• SN74ACT36411024 × 36CLOCKED FIRST-IN, FIRST-OUT MEMORYSCAS338C – JANUARY 1994 – REVISED OCTOBER 1997TYPICAL CHARACTERISTICSSUPPLY CURRENTvsCLOCK FREQUENCY250fdata = 1/2 fclockTA = 25°CCL = 0 pFVCC = 5 V150VCC = 4.5 V100VCC = 5.5 VI C C ( f ) – Supply Current – mA200500010203040506070fclock – Clock Frequency – MHzFigure 17calculating power dissipationThe ICC(f) current in Figure 17 was taken while simultaneously reading and writing the FIFO on theSN74ACT3641 with CLKA and CLKB set to fclock. All data inputs and data outputs change state during eachclock cycle to consume the highest supply current. Data outputs are disconnected to normalize the graph to azero-capacitance load. Once the capacitive load per data-output channel and the number of SN74ACT3641inputs driven by TTL high levels are known, the power dissipation can be calculated with the equation below.With ICC(f) taken from Figure 17, the maximum power dissipation (PT) of the SN74ACT3641 can be calculatedby:PT = VCC × [ICC(f) + (N × ∆ICC × dc)] + ∑(CL × VCC2 × fo)where:N∆ICCdcCLfo=====number of inputs driven by TTL levelsincrease in power-supply current for each input at a TTL high levelduty cycle of inputs at a TTL high level of 3.4 Voutput capacitive loadswitching frequency of an outputWhen no reads or writes are occurring on the SN74ACT3641, the power dissipated by a single clock (CLKAor CLKB) input running at frequency fclock is calculated by:PT = VCC × fclock × 0.29 mA/MHzPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•25PACKAGEOPTIONADDENDUM
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13-Oct-2009
PACKAGINGINFORMATION
OrderableDeviceSN74ACT3641-15PCBSN74ACT3641-15PQSN74ACT3641-20PCBSN74ACT3641-20PQ
(1)
Status(1)ACTIVEACTIVEACTIVEACTIVE
PackageTypeHLQFPBQFPHLQFPBQFP
PackageDrawingPCBPQPCBPQ
PinsPackageEcoPlan(2)
Qty120132120132
90369036
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU
MSLPeakTemp(3)Level-3-260C-168HRLevel-4-260C-72HRLevel-3-260C-168HRLevel-4-260C-72HR
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
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OTHERQUALIFIEDVERSIONSOFSN74ACT3641:•Military:SN54ACT3641
NOTE:QualifiedVersionDefinitions:
•Military-QMLcertifiedforMilitaryandDefenseApplications
Addendum-Page1
MECHANICAL DATA MBQF001A – NOVEMBER 1995PQ (S-PQFP-G***) 100 LEAD SHOWN13110089PLASTIC QUAD FLATPACK14880.012 (0,30)0.008 (0,20)”D3” SQ0.006 (0,15)M0.025 (0,635)640.150 (3,81)0.130 (3,30)39”D1” SQ”D” SQ”D2” SQ0.020 (0,51) MIN0.010 (0,25)0°–8°0.046 (1,17)0.036 (0,91)Seating Plane0.180 (4,57) MAXLEADS ***DIM”D”MAXMINMAXMINMAXMINNOM1000.890 (22,61)0.870 (22,10)0.766 (19,46)0.734 (18,64)0.912 (23,16)0.888 (22,56)0.600 (15,24)0.004 (0,10)63Gage Plane0.006 (0,16) NOM381321.090 (27,69)1.070 (27,18)0.966 (24,54)0.934 (23,72)1.112 (28,25)1.088 (27,64)0.800 (20,32)4040045/C 11/95”D1””D2””D3”NOTES:A.All linear dimensions are in inches (millimeters).B.This drawing is subject to change without notice.C.Falls within JEDEC MO-069POST OFFICE BOX 655303 DALLAS, TEXAS 75265• MHTQ004A – JANUARY 1995 – REVISED JANUARY 1998 MECHANICAL DATA PCB (S-PQFP-G120) 0,230,1361PLASTIC QUAD FLATPACK (DIE DOWN)0,40900,07MHeat Slug9160120310,13 NOM111,60 TYP14,20SQ13,8016,20SQ15,801,451,3530Gage Plane0,05 MIN0,250°–7°0,750,45Seating Plane1,60 MAX0,084040202/C 12/96NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Thermally enhanced molded plastic package with a heat slug (HSL)Falls within JEDEC MS-026POST OFFICE BOX 655303 DALLAS, TEXAS 75265•IMPORTANTNOTICE
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applicationsusingTIcomponents.Tominimizetherisksassociatedwithcustomerproductsandapplications,customersshouldprovideadequatedesignandoperatingsafeguards.
TIdoesnotwarrantorrepresentthatanylicense,eitherexpressorimplied,isgrantedunderanyTIpatentright,copyright,maskworkright,orotherTIintellectualpropertyrightrelatingtoanycombination,machine,orprocessinwhichTIproductsorservicesareused.InformationpublishedbyTIregardingthird-partyproductsorservicesdoesnotconstitutealicensefromTItousesuchproductsorservicesorawarrantyorendorsementthereof.Useofsuchinformationmayrequirealicensefromathirdpartyunderthepatentsorotherintellectualpropertyofthethirdparty,oralicensefromTIunderthepatentsorotherintellectualpropertyofTI.
ReproductionofTIinformationinTIdatabooksordatasheetsispermissibleonlyifreproductioniswithoutalterationandisaccompaniedbyallassociatedwarranties,conditions,limitations,andnotices.Reproductionofthisinformationwithalterationisanunfairanddeceptivebusinesspractice.TIisnotresponsibleorliableforsuchaltereddocumentation.Informationofthirdpartiesmaybesubjecttoadditionalrestrictions.
ResaleofTIproductsorserviceswithstatementsdifferentfromorbeyondtheparametersstatedbyTIforthatproductorservicevoidsallexpressandanyimpliedwarrantiesfortheassociatedTIproductorserviceandisanunfairanddeceptivebusinesspractice.TIisnotresponsibleorliableforanysuchstatements.
TIproductsarenotauthorizedforuseinsafety-criticalapplications(suchaslifesupport)whereafailureoftheTIproductwouldreasonablybeexpectedtocauseseverepersonalinjuryordeath,unlessofficersofthepartieshaveexecutedanagreementspecificallygoverningsuchuse.Buyersrepresentthattheyhaveallnecessaryexpertiseinthesafetyandregulatoryramificationsoftheirapplications,and
acknowledgeandagreethattheyaresolelyresponsibleforalllegal,regulatoryandsafety-relatedrequirementsconcerningtheirproductsandanyuseofTIproductsinsuchsafety-criticalapplications,notwithstandinganyapplications-relatedinformationorsupportthatmaybeprovidedbyTI.Further,BuyersmustfullyindemnifyTIanditsrepresentativesagainstanydamagesarisingoutoftheuseofTIproductsinsuchsafety-criticalapplications.
TIproductsareneitherdesignednorintendedforuseinmilitary/aerospaceapplicationsorenvironmentsunlesstheTIproductsarespecificallydesignatedbyTIasmilitary-gradeor\"enhancedplastic.\"OnlyproductsdesignatedbyTIasmilitary-grademeetmilitary
specifications.BuyersacknowledgeandagreethatanysuchuseofTIproductswhichTIhasnotdesignatedasmilitary-gradeissolelyattheBuyer'srisk,andthattheyaresolelyresponsibleforcompliancewithalllegalandregulatoryrequirementsinconnectionwithsuchuse.TIproductsareneitherdesignednorintendedforuseinautomotiveapplicationsorenvironmentsunlessthespecificTIproductsaredesignatedbyTIascompliantwithISO/TS16949requirements.Buyersacknowledgeandagreethat,iftheyuseanynon-designatedproductsinautomotiveapplications,TIwillnotberesponsibleforanyfailuretomeetsuchrequirements.
FollowingareURLswhereyoucanobtaininformationonotherTexasInstrumentsproductsandapplicationsolutions:ProductsAmplifiers
DataConvertersDLP®ProductsDSP
ClocksandTimersInterfaceLogic
PowerMgmtMicrocontrollersRFID
RF/IFandZigBee®Solutions
amplifier.ti.comdataconverter.ti.comwww.dlp.comdsp.ti.comwww.ti.com/clocksinterface.ti.comlogic.ti.compower.ti.commicrocontroller.ti.comwww.ti-rfid.comwww.ti.com/lprfApplicationsAudio
AutomotiveBroadbandDigitalControlMedicalMilitary
OpticalNetworkingSecurityTelephony
Video&ImagingWireless
www.ti.com/audiowww.ti.com/automotivewww.ti.com/broadbandwww.ti.com/digitalcontrolwww.ti.com/medicalwww.ti.com/militarywww.ti.com/opticalnetworkwww.ti.com/securitywww.ti.com/telephonywww.ti.com/videowww.ti.com/wirelessMailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265
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