Semiconductor chip package with interconnect layer

专利名称：Semiconductor chip package with

interconnect layers and routing and testingmethods

发明人：Mark P. Stager,Abraham F. Yee,Gobi R.

Padmanabhan

申请号：US08/647344申请日：19960509公开号：US05777383A公开日：19980707

摘要：A package for a semiconductor chip is provided which incorporates a plurality oflevels of interconnect--conductive layers within the package which selectively directsignals to and from pins of the die and/or the pins of the package. A single generalpurpose chip may thus be fabricated in large quantities with the interconnect of thepackage used to define the specific purpose, functionality and pinout of the final device.Similarly, a standard package may be built to work with a large class of different chipsand only the interconnect layers in the package need to be modified to allow thepackage to work with each different chip. In a second aspect of the invention, one ormore layers of interconnect in the package may contain active electronic componentswhich may be connected to nodes of the chip through the interconnect of the packageand through the pins of the die. Accordingly, devices which are difficult or impossible toincorporate into a semiconductor die may be incorporated into a single package alongwith the die. In a third aspect of the invention, a method of integrated circuit designincludes using a conventional CAD design tool software package to design not only the

integrated circuit, but also variable circuit elements (such as interconnect and electroniccomponents) embedded in the chip package. In a fourth aspect of the invention, a testingmethodology for wafer die subcomponents is provided.

申请人：LSI LOGIC CORPORATION

代理机构：D'Alessandro & Ritchie

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