EDA流水灯底层文件代码

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity div is

PORT( CLK_IN: IN STD_LOGIC;--输入时钟信号

CLK_OUT: OUT STD_LOGIC--分频后的输出时钟信号

);

end div;

architecture Behavioral of div is

signal cont: STD_logic_vector(1 downto 0);

begin

process(CLK_IN)

BEGIN

IF RISING_EDGE(CLK_IN) THEN

IF CONT=\"11\" THEN

CONT<=\"00\";

CLK_OUT<='1';

ELSE CONT<=CONT+'1';

CLK_OUT<='0';

END IF;

END IF;

END PROCESS;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity led0 is

PORT(CLK :IN STD_LOGIC;--分频后的时钟信号

EN :IN STD_LOGIC;--使能控制信号

M :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--控制8个灯的输出信号

);

end led0;

architecture Behavioral of led0 is

SIGNAL SEL : STD_LOGIC_VECTOR(2 DOWNTO 0);

begin

PROCESS(EN,CLK,SEL)

BEGIN

IF RISING_EDGE(CLK) THEN

IF EN='1' THEN

IF SEL=\"111\" THEN

SEL<=\"000\";

ELSE

SEL<=SEL+'1';

END IF;

END IF;

END IF;

CASE SEL IS

WHEN \"000\" =>M<=\"10000000\";

WHEN \"001\" =>M<=\"01000000\";

WHEN \"010\" =>M<=\"00100000\";

WHEN \"011\" => M<=\"00010000\";

WHEN \"100\" => M<=\"00001000\";

WHEN \"101\" =>M<=\"00000100\";

WHEN \"110\" =>M<=\"00000010\";

WHEN \"111\" => M<=\"00000001\";

WHEN OTHERS =>NULL;

END CASE;

END PROCESS;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity led1 is

PORT(CLK :IN STD_LOGIC;--分频后的时钟信号

EN :IN STD_LOGIC;--使能控制信号

N :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--控制8个灯的输出信号

);

end led1;

architecture Behavioral of led1 is

SIGNAL SEL : STD_LOGIC_VECTOR(2 DOWNTO 0);

begin

PROCESS(EN,CLK,SEL)

BEGIN

IF RISING_EDGE(CLK) THEN

IF EN='1' THEN

IF SEL=\"111\" THEN

SEL<=\"000\";

ELSE

SEL<=SEL+'1';

END IF;

END IF;

END IF;

CASE SEL IS

WHEN \"000\" =>N<=\"00000001\";

WHEN \"001\" =>N<=\"00000010\";

WHEN \"010\" =>N<=\"00000100\";

WHEN \"011\" =>N<=\"00001000\";

WHEN \"100\" =>N<=\"00010000\";

WHEN \"101\" =>N<=\"00100000\";

WHEN \"110\" =>N<=\"01000000\";

WHEN \"111\" =>N<=\"10000000\";

WHEN OTHERS =>NULL;

END CASE;

END PROCESS;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity led2 is

PORT(CLK :IN STD_LOGIC;--分频后的时钟信号

EN :IN STD_LOGIC;--使能控制信号

L :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--控制8个灯的输出信号

);

end led2;

architecture Behavioral of led2 is

SIGNAL SEL : STD_LOGIC_VECTOR(2 DOWNTO 0);

begin

PROCESS(EN,CLK,SEL)

BEGIN

IF RISING_EDGE(CLK) THEN

IF EN='1' THEN

IF SEL=\"111\" THEN

SEL<=\"000\";

ELSE

SEL<=SEL+'1';

END IF;

END IF;

END IF;

CASE SEL IS

WHEN \"000\" =>L<=\"10000001\";

WHEN \"001\" =>L<=\"01000010\";

WHEN \"010\" =>L<=\"00100100\";

WHEN \"011\" =>L<=\"00011000\";

WHEN \"100\" =>L<=\"00100100\";

WHEN \"101\" =>L<=\"01000010\";

WHEN \"110\" =>L<=\"10000001\";

WHEN \"111\" =>L<=\"11111111\";

WHEN OTHERS =>NULL;

END CASE;

END PROCESS;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity led3 is

PORT(CLK :IN STD_LOGIC;--分频后的时钟信号

EN :IN STD_LOGIC;--使能控制信号

Q :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--控制8个灯的输出信号

);

end led3;

architecture Behavioral of led3 is

SIGNAL SEL : STD_LOGIC_VECTOR(2 DOWNTO 0);

begin

PROCESS(EN,CLK,SEL)

BEGIN

IF RISING_EDGE(CLK) THEN

IF EN='1' THEN

IF SEL=\"111\" THEN

SEL<=\"000\";

ELSE

SEL<=SEL+'1';

END IF;

END IF;

END IF;

CASE SEL IS

WHEN \"000\" => Q <=\"10100000\";

WHEN \"001\" => Q <=\"01010000\";

WHEN \"010\" => Q <=\"00101000\";

WHEN \"011\" => Q <=\"00010100\";

WHEN \"100\" => Q <=\"00001010\";

WHEN \"101\" => Q <=\"00000101\";

WHEN \"110\" => Q <=\"00001010\";

WHEN \"111\" => Q <=\"00001010\";

WHEN OTHERS =>NULL;

END CASE;

END PROCESS;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux41 is

PORT( a,b,c,d: IN STD_LOGIC;

din: IN STD_LOGIC_vector(1 downto 0);

dout: OUT STD_LOGIC

);

end mux41;

architecture Behavioral of mux41 is

signal sel: STD_LOGIC_vector(1 downto 0);

begin

process(a,b,c,d,din)

BEGIN

case sel is

when \"00\"=>dout<=a; when \"01\"=>dout<=b;

when \"10\"=>dout<=c; when \"11\"=>dout<=d;

when others=>null;

END case;

END PROCESS;

end Behavioral;