SBAS226 – MARCH 2002
16-Bit, High-Speed, 2.7V to 5.5V microPower SamplingANALOG-TO-DIGITAL CONVERTER
FEATURES
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16-BITS NO MISSING CODESVERY LOW NOISE: 3LSBp-p
EXCELLENT LINEARITY: ±1.5LSB typmicroPOWER: 4.5mW at 100kHz
1mW at 10kHz
MSOP-8 PACKAGE
16-BIT UPGRADE TO THE 12-BIT ADS7816AND ADS7822
PIN-COMPATIBLE WITH THE ADS7816,ADS7822, AND ADS8320
SERIAL (SPI™/SSI) INTERFACE
DESCRIPTION
The ADS8325 is a 16-bit, sampling, Analog-to-Digital (A/D)converter specified for a supply voltage range from 2.7V to5.5V. It requires very little power, even when operating at thefull 100kHz data rate. At lower data rates, the high speed ofthe device enables it to spend most of its time in the power-down mode. For example, the average power dissipation isless than 1mW at a 10kHz data rate.
The ADS8325 offers excellent linearity and very low noiseand distortion. It also features a synchronous serial (SPI/SSIcompatible) interface and a differential input. The referencevoltage can be set to any level within the range of 2.5V toVDD.
Low power and small size make the ADS8325 ideal forportable and battery-operated systems. It is also a perfect fitfor remote data acquisition modules, simultaneous multi-channel systems, and isolated data acquisition. The ADS8325is available in an MSOP-8 package.
APPLICATIONS
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BATTERY-OPERATED SYSTEMSREMOTE DATA ACQUISITIONISOLATED DATA ACQUISITION
SIMULTANEOUS SAMPLING, MULTI-CHANNELSYSTEMS
qINDUSTRIAL CONTROLSqROBOTICS
qVIBRATION ANALYSIS
SPI is a registered trademark of Motorola.SARREFADS8325DOUT+INCDAC–INS/H AmpComparatorCS/SHDNSerialInterfaceDCLOCKPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 2002, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS(1)
Absolute Maximum Ratings over operating free-air temperature, unless other-wise noted.
Supply Voltage, DGND to VDD..................................................................–0.3V to 6VAnalog Input Voltage(2)...............................................................–0.3V to VDD + 0.3VReference Input Voltage(2)........................................................–0.3V to VDD + 0.3VDigital Input Voltage(2)............................................................. –0.3V to VDD + 0.3VInput Current to Any Pin Except Supply.........................–20mA to 20mAPower Dissipation.......................................See Dissipation Rating TableOperating Virtual Junction Temperature Range, TJ......–40°C to +150°COperating Free-Air Temperature Range, TA....................–40°C to +85°CStorage Temperature Range, TSTG................................–65°C to +150°CLead Temperature 1.6mm (1/16 inch) from Case for 10sec.....................260°CNOTES: (1) Stresses beyond those listed under \"absolute maximum ratings\"may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond thoseindicated under \"recommended operating conditions\" is not implied. Exposureto absolute-maximum-rated conditions of extended periods may affect devicereliability. (2) All voltage values are with respect to ground terminal.
ELECTROSTATICDISCHARGE SENSITIVITYThis integrated circuit can be damaged by ESD. TexasInstruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper han-dling and installation procedures can cause damage.ESD damage can range from subtle performance degrada-tion to complete device failure. Precision integrated circuitsmay be more susceptible to damage because very smallparametric changes could cause the device not to meet itspublished specifications.
PACKAGE/ORDERING INFORMATION
MAXIMUMNOINTEGRALMISSINGLINEARITYCODES ERRORERROR (LSB) (LSB)(1)
±6
SPECIFIED
PACKAGE-PACKAGETEMPERATURE
LEADDESIGNATOR(2)RANGEMSOP-8
PRODUCTADS8325I
PACKAGE
MARKING
B25
ORDERINGNUMBERADS8325IDGKTADS8325IDGKRADS8325IBDGKTADS8325IBDGKR
TRANSPORTMEDIA, QUANTITYTape and Reel, 250Tape and Reel, 2500Tape and Reel, 250Tape and Reel, 2500
\"\"
\"\"
15
\"\"
\"\"
DGK
\"\"
–40°C to 85°C
\"\"
\"\"
ADS8325IB±416MSOP-8DGK–40°C to 85°CB25
NOTE: (1) No Missing Codes Error specifies a 5V power supply and reference voltage. (2) For the most current specifications and package information, refer toour web site at www.ti.com.
PACKAGE DISSIPATION RATING TABLE
PACKAGEDGK
RθJC39.1°C/W
RθJA206.3°C/W
DERATING FACTORABOVE TA = 25°C
4.847mW/°C
TA ≤ 25°CPOWER RATING
606mW
TA = 70°CPOWER RATING
388mW
TA = 85°CPOWER RATING
315mW
EQUIVALENT INPUT CIRCUIT
VDDRON 20ΩANALOG INC(SAMPLE)20pFREF5kΩGNDDiode Turn-On Voltage: 0.35VEquivalent Analog Input CircuitGNDEquivalent ReferenceInput CircuitGNDEquivalent Digital Input/Output CircuitVDDShut-DownSwitchVDD20pFI/ORECOMMENDED OPERATING CONDITIONS
MIN
Supply VoltageGND to VDDAnalog InputVoltage
Low-Voltage Levels5V Logic Levels
2.74.52.5–0.30–40
0TYP5.0
MAX3.65.5VDD0.5VREF125
UNITVVVVV°C
Reference Input Voltage
–IN
+IN – (–IN)
Operating Junction TemperatureRange, TJ
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ADS8325
SBAS226
ELECTRICAL CHARACTERISTICS: VDD = +5V
Over recommended operating free-air temperature at –40°C to +85°C, VREF = +5V, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise noted.
ADS8325IPARAMETERANALOG INPUTFull-Scale RangeOperating Common-Mode SignalInput ResistanceInput CapacitanceInput Leakage CurrentDifferential Input CapacitanceFull-Power BandwithDC ACCURACYResolutionNo Missing CodeIntegral Linearity ErrorOffset ErrorOffset Error DriftGain ErrorGain Error DriftNoisePower-Supply RejectionSAMPLING DYNAMICSConversion TimeAcquisition TimeThroughout RateClock FrequencyAC ACCURACYTotal Harmonic DistortionSpurious-Free Dynamic RangeSignal-to-Noise RatioSignal-to-Noise + DistortionEffective Number of BitsVOLTAGE REFERENCE INPUTReference VoltageReference Input ResistanceReference Input CapacitanceReference Input CurrentCS = VDDDIGITAL INPUTS(1)Logic FamilyHigh-Level Input VoltageLow-Level Input VoltageInput CurrentInput CapacitanceDIGITAL OUTPUTS(1)Logic FamilyHigh-Level Output VoltageLow-Level Output VoltageHigh-Impedance-State Output CurrentOutput CapacitanceLoad CapacitanceData FormatFSRCONDITIONS+IN – (–IN)–IN = GND–IN = GND, During Sampling–IN = GND+IN to –IN, During SamplingfS Sinewave, SINAD at –3dB1615±3±0.75±0.2±0.32036.6671.8750.024THDSFDRSNRSINADENOB5Vp-p Sinewave, at 1kHz5Vp-p Sinewave, at 1kHz5Vp-p Sinewave, at 1kHz–100–100–90–9014.62.5CS = GND, fSAMPLE = 0HzCS = VDD552010.1CMOSVIHVILIINCI0.7 • VDD–0.3VI = VDD or GND5CMOSVOHVOLIOZCOCLVDD = 4.5V, IOH = –100µAVDD = 4.5V, IOL = 100µACS = VDD, VI = VDD or GND4.440.5±50530Straight Binary✻✻✻✻✻✻VDD + 0.30.3 • VDD±50✻✻✻✻VVnApFpFVDD + 0.3✻✻✻✻✻✻✻✻✻VVnApF666.71002.4✻✻✻–106–108–91–9114.7✻±6±1.5±24✻✻✻✻✻✻MIN0–0.3545±502020✻16±1.5±0.5✻±4±1±12TYPMAXVREF0.5MIN✻✻✻✻✻✻✻ADS8325IBTYPMAX✻✻UNITSVVGΩpFnApFkHzBitsBitsLSBmVppm/°CLSBppm/°CµVRMSLSBµsµskSPSMHzdBdBdBdBBitsVkΩGΩpFmAµAFSBWNMCINLVOSTCVOSGERRTCGERR4.75V ≤ VDD ≤ 5.25tCONVtAQ24kHz < fCLK ≤ 2.4MHzfCLK = 2.4MHz1.5✻✻✻ indicates the same specifications as the ADS8325I.
NOTE: (1) Applies for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V.
ADS8325
SBAS226
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3
ELECTRICAL CHARACTERISTICS: VDD = +2.7V
Over recommended operating free-air temperature at –40°C to +85°C, VREF = +2.5V, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise noted.
ADS8325IPARAMETERANALOG INPUTFull-Scale RangeOperating Common-Mode SignalInput ResistanceInput CapacitanceInput Leakage CurrentDifferential Input CapacitanceFull-Power BandwithDC ACCURACYResolutionNo Missing CodeIntegral Linearity ErrorOffset ErrorOffset Error DriftGain ErrorGain Error DriftNoisePower-Supply RejectionSAMPLING DYNAMICSConversion TimeAcquisition TimeThroughout RateClock FrequencyAC ACCURACYTotal Harmonic DistortionSpurious-Free Dynamic RangeSignal-to-Noise RatioSignal-to-Noise + DistortionEffective Number of BitsVOLTAGE REFERENCE INPUTReference VoltageReference Input ResistanceReference Input CapacitanceReference Input CurrentCS = VDDDIGITAL INPUTS(1)Logic FamilyHigh-Level Input VoltageVIHLow-Level Input VoltageVILInput Current IINInput CapacitanceCIDIGITAL OUTPUTS(1)Logic FamilyHigh-Level Output VoltageLow-Level Output VoltageHigh-Impedance-State Output CurrentOutput CapacitanceLoad CapacitanceData FormatLVCMOSVOHVOLIOZCOCLVDD = 2.7V, IOH = –100µAVDD = 2.7V, IOL = 100µACS = VDD, VI = VDD or GNDVDD – 0.20.2±50530Straight Binary✻✻✻✻✻✻✻✻VVnApFpFFSRCONDITIONS+IN – (–IN)–IN = GND–IN = GND, During Sampling–IN = GND+IN to –IN, During SamplingfS Sinewave, SINAD at –3dB16NMCINLVOSTCVOSGERRTCGERR2.7V ≤ VDD ≤ 3.6VtCONVtAQ24kHz < fCLK ≤ 2.4MHzfCLK = 2.4MHz6.6671.8750.024THDSFDRSNRSINADENOB2.5Vp-p Sinewave, at 1kHz2.5Vp-p Sinewave, at 1kHz2.5Vp-p Sinewave, at 1kHz–94–96–85–8513.82.5CS = GND, fSAMPLE = 0HzCS = VDD55200.50.1LVCMOSVDD = 3.6VVDD = 2.7VVI = VDD or GND2–0.35VDD + 0.30.8±50✻✻✻✻VDD + 0.3✻✻✻✻✻✻✻✻✻✻VVnApF14±3±0.75±3±33±0.3207±6±1.5MIN0–0.3545±50204✻15±1.5±0.5✻±16✻✻✻±4±1TYPMAXVREF0.5MIN✻✻✻✻✻✻✻BitsBitsLSBmVppm/°CLSBppm/°CµVRMSLSBµsµskSPSMHz✻✻–86–85.513.9✻dBdBdBdBBitsVkΩGΩpFmAµAADS8325IBTYPMAX✻✻UNITSVVGΩpFnApFkHzFSBW666.71002.40.75✻✻ indicates the same specifications as the ADS8325I.
NOTE: (1) Applies for 3.0V nominal supply: VDD (min) = 2.7V and VDD (max) = 3.6V.
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ADS8325
SBAS226
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature at –40°C to 85°C, VREF = VDD, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise noted.
ADS8325I
PARAMETER
POWER-SUPPLY REQUIREMENTSPower Supply (VDD)
Operating Supply Current (IDD)Power-Down Supply Current (IDD)Power Dissipation
Power Dissipation in Power-Down
✻ indicates the same specifications as the ADS8325I.
CONDITIONSLow-Voltage Levels5V Logic Levels
VDD = 3VVDD = 5VVDD = 3VVDD = 5VVDD = 3VVDD = 5V
VDD = 3V, CS = VDDVDD = 5V, CS = VDD
MIN2.74.5
0.750.90.10.22.254.50.30.6TYP
MAX3.65.51.51.5
MIN✻✻
✻✻✻✻✻✻✻✻ADS8325IB
TYP
MAX✻✻✻✻
UNITSVVmAmAµAµAmWmWµWµW
4.57.5✻✻
PIN CONFIGURATION
Top View
MSOP
PIN DESCRIPTIONS
NAMEREF+IN–INGNDCS/SHDNDOUTDCLOCKVDD
PIN12345678
I/OAIAIAIPDIDODIP
DESCRIPTION
Reference InputNoninverting InputInverting Analog InputGround
Chip Select when LOW, Shutdown Mode whenHIGH.
The serial output data word.
Data Clock synchronizes the serial data transferand determines conversion speed.Power Supply
REF+IN–INGND1234ADS83258765+VDDDCLOCKDOUTCS/SHDNTIMING CHARACTERISTICS
SYMBOLtSMPLtCONVtCYCtCSDtSUCStHDOtDIStENtFtR
DESCRIPTION
Analog Input Sample TimeConversion TimeThroughput Rate
CS Falling to DCLOCK LOWCS Falling to DCLOCK Rising
DCLOCK Falling to Current DOUT Not ValidCS Rising to DOUT Tri-StateDCLOCK Falling to DOUT EnabledDOUT Fall TimeDOUT Rise Time
NOTE: AI is Analog Input, DI is Digital Input, DO is Digital Output, and P isPower-Supply Connection.
MIN4.5
TYP16
MAX5.01000
UNITSClk CyclesClk Cycles
kHznsnsns
205
15702057
100502525
nsnsnsns
TIMING DIAGRAMS
Complete CycleCS/SHDNtSUCSSampleDCLOCKtCSDDOUTHi-Z0Use positive clock edge for data transferB15B14B13B12B11B10B9B8(MSB)tCONVB7B6B5B4B3B2B1B0(LSB)Hi-ZConversionPower DowntSMPLNOTE: A minimum of 22 clock cycles are required for 16-bit conversion. Shown are 24 clock cycles.If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.ADS8325
SBAS226
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5
TIMING DIAGRAMS (Cont.)
Timing Diagrams and Test Circuits for the Parameters in the Timing Characteristics table.1.4V3kΩDOUT100pFCLOADTest PointDOUTtrtf90%10%Voltage Waveforms for DOUT Rise and Fall Times, tr, tfLoad Circuit for tdDO, tr, and tfTest PointDCLOCKtdDODOUTthDOVoltage Waveforms for DOUT Delay Times, tdDODOUT3kΩ100pFCLOADLoad Circuit for tdis and tenVCCtdis Waveform 2, tentdis Waveform 1CS/SHDN90%CS/SHDNDCLOCK145DOUTWaveform 1(1)tdisDOUTWaveform 2(2)Voltage Waveforms for tdis90%10%DOUTtenVoltage Waveforms for tenB15NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control.6
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ADS8325
SBAS226
TYPICAL CHARACTERISTICS: VDD = +5V
At TA = 25°C, VDD = +5V, VREF = +5V, fSAMPLE = 100kHz, fCLK = 24 • fSAMPLE, unless otherwise noted.
3210–1–2–30000HINTEGRAL LINEARITY ERROR vs CODE321DLE(LSBS)DIFFERENTIAL LINEARITY ERROR vs CODEILE(LSBS)0–1–2–30000H4000H8000HOutput CodeC000HFFFFH4000H8000HOutput CodeC000HFFFFH0–20–40FREQUENCY SPECTRUM(8192 point FFT, FIN = 1.0132kHz, –0.2dB)0–20–40FREQUENCY SPECTRUM(8192 point FFT, FIN = 10.0022kHz, –0.2dB)Amplitude (dB)–60–80–100–120–140–16001020304050Frequency (kHz)Amplitude (dB)–60–80–100–120–140–16001020304050Frequency (kHz)105100SIGNAL-TO-NOISE RATIO ANDSIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY110105100SPURIOUS-FREE DYNAMIC RANGE ANDTOTAL HARMONIC DISTORTION vs INPUT FREQUENCYSFDR–110–105–100SNRSNR and SINAD (dB)95SFDR (dB)8580757065110Frequency (kHz)100245SINAD9085807570110Frequency (kHz)100NOTE: (1) First nine harmonics of the input frequency.THD(1)–90–85–80–75–70245ADS8325
SBAS226
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THD (dB)9095–957
TYPICAL CHARACTERISTICS: VDD = +5V (Cont.)
At TA = 25°C, VDD = +5V, VREF = +5V, fSAMPLE = 100kHz, fCLK = 24 • fSAMPLE, unless otherwise noted.
100Signal-to-Noise + Distortion (dB)SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVELFIN = 1.0132kHz15.014.5EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY908070605040302010–80Effective Number of Bits14.013.513.012.512.011.511.0110Frequency (kHz)100–70–60–50–40–30–20–100Input Level (dB)0.40.2CHANGE IN SIGNAL-TO-NOISE + DISTORTIONvs TEMPERATUREFIN = 1.0132kHz, –0.2dBDelta from 25°C (LSBS)2.01.51.00.50.0–0.5–1.0–1.5
CHANGE IN GAIN vs TEMPERATUREDelta from 25°C (dB)0.0–0.2–0.4–0.6–0.8–50–250255075100Temperature (°C)–50–250255075100Temperature (°C)3.02.5Delta from 25°C (LSBS)CHANGE IN UPO vs TEMPERATURE1.1SUPPLY CURRENT vs TEMPERATURE1.51.00.50.0–0.5–1.0–50Supply Current (mA)2.01.00.90.80.7–250255075100–50–250255075100Temperature (°C)Temperature (°C)8
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ADS8325
SBAS226
TYPICAL CHARACTERISTICS: VDD = +2.7V
At TA = 25°C, VDD = 2.7V, VREF = 2.5V, fSAMPLE = 100kHz, fCLK = 24 • fSAMPLE, unless otherwise noted.
321INTEGRAL LINEARITY ERROR vs CODE321DLE(LSBS)DIFFERENTIAL LINEARITY ERROR vs CODEILE(LSBS)0–1–2–30000H0–1–2–30000H4000H8000HOutput CodeC000HFFFFH4000H8000HOutput CodeC000HFFFFH0–20–40FREQUENCY SPECTRUM(8192 point FFT, FIN = 1.0132kHz, –0.2dB)0–20–40FREQUENCY SPECTRUM(8192 point FFT, FIN = 10.0022kHz, –0.2dB)Amplitude (dB)–60–80–100–120–140–16001020304050Frequency (kHz)Amplitude (dB)–60–80–100–120–140–16001020304050Frequency (kHz)95SIGNAL-TO-NOISE RATIO ANDSIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY1009080SPURIOUS FREE DYNAMIC RANGE ANDTOTAL HARMONIC DISTORTION vs INPUT FREQUENCY–100–9085SNRSNR and SINAD (dB)SFDR–80–70–6070605040NOTE: (1) First nineharmonics of the input frequency.1THD(1)6555SINAD–50–4045110Frequency (kHz)10024510Frequency (kHz)100245ADS8325
SBAS226
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THD (dB)75SFDR (dB)TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.)
At TA = 25°C, VDD = 2.7V, VREF = 2.5V, fSAMPLE = 100kHz, fCLK = 24 • fSAMPLE, unless otherwise noted.
100SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVELFIN = 1.0132kHzSignal-to-Noise + Distortion (dB)908070605040302010–8014.514.013.513.012.512.011.511.010.510.09.59.08.58.07.57.01EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCYEffective Number of Bits–70–60–50–40–30–20–10010Frequency (kHz)100Input Level (dB)0.40.2CHANGE IN SIGNAL-TO-NOISE + DISTORTIONvs TEMPERATUREFIN = 1.0132kHz, –0.2dBDelta from 25°C (LSBS)2.01.51.00.50.0–0.5–1.0–1.5–2.0
–50
CHANGE IN GAIN vs TEMPERATUREDelta from 25°C (dB)0.0–0.2–0.4–0.6–0.8–50–250255075100Temperature (°C)–250255075100Temperature (°C)1.2CHANGE IN UPO vs TEMPERATURE0.9SUPPLY CURRENT vs TEMPERATUREDelta from 25°C (LSBS)0.8Supply Current (mA)0.80.40.00.7–0.4–0.8–500.6–250255075100–50–250255075100Temperature (°C)Temperature (°C)10
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ADS8325
SBAS226
THEORY OF OPERATION
The ADS8325 is a classic Successive Approximation Register(SAR) Analog-to-Digital (A/D) converter. The architecture is basedon capacitive redistribution that inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µ CMOSprocess. The architecture and process allow the ADS8325 toacquire and convert an analog signal at up to 100,000 conver-sions per second while consuming less than 4.5mW from +VDD.The ADS8325 requires an external reference, an external clock,and a single power source (VDD). The external reference can beany voltage between 2.5V and 5.5V. The value of the referencevoltage directly sets the range of the analog input. The referenceinput current depends on the conversion rate of the ADS8325.The external clock can vary between 24kHz (1kHz throughput)and 2.4MHz (100kHz throughput). The duty cycle of the clock isessentially unimportant as long as the minimum high and lowtimes are at least 200ns (VDD = 4.75V or greater). The minimumclock frequency is set by the leakage on the internal capacitorsto the ADS8325.
The analog input is provided to two input pins: +IN and –IN. Whena conversion is initiated, the differential input on these pins issampled on the internal capacitor array. While a conversion is inprogress, both inputs are disconnected from any internal function.The digital result of the conversion is clocked out by the DCLOCKinput and is provided serially, most significant bit first, on the DOUTpin. The digital data that is provided on the DOUT pin is for theconversion currently in progress—there is no pipeline delay. It ispossible to continue to clock the ADS8325 after the conversionis complete and to obtain the serial data least significant bit first.See the Digital Timing section for more information.
The range of the –IN input is limited to –0.3V to +0.5V. Dueto this, the differential input could be used to reject signalsthat are common to both inputs in the specified range. Thus,the –IN input is best used to sense a remote signal groundthat may move slightly with respect to the local groundpotential.
The general method for driving the analog input of theADS8325 is shown in Figures 1 and 2. The –IN input is heldat the common-mode voltage. The +IN input swings from–IN (or common-mode voltage) to –IN + VREF (or common-mode voltage + VREF), and the peak-to-peak amplitude is+VREF. The value of VREF determines the range over whichthe common-mode voltage may vary (see Figure 3). Figures5 and 6 illustrate the typical change in gain and offset as afunction of the common-mode voltage applied to the –IN pin.
0V to +VREFPeak-to-PeakCommon-ModeVoltageADS8325FIGURE 2. Methods of Driving the ADS8325
The input current required by the analog inputs depends ona number of factors: sample rate, input voltage, sourceimpedance, and power-down mode. Essentially, the currentinto the ADS8325 charges the internal capacitor array duringthe sample period. After this capacitance has been fullycharged, there is no further input current. The source of theanalog input voltage must be able to charge the inputcapacitance (20pF) to a 16-bit settling level within 4.5 clockcycles (1.875µs). When the converter goes into the holdmode, or while it is in the power-down mode, the inputimpedance is greater than 1GΩ.
ANALOG INPUT
The analog input of ADS8325 is differential. The +IN and–IN input pins allow for a differential input signal. Theamplitude of the input is the difference between the +IN and–IN input, or (+IN) – (–IN). Unlike some converters of thistype, the –IN input is not resampled later in the conversioncycle. When the converter goes into the hold mode orconversion, the voltage difference between +IN and –IN iscaptured on the internal capacitor array.
Common-Mode Voltage + VREF+VREF+IN Common-Mode Voltaget–IN = Common-Mode VoltageNOTE: The maximum differential voltage between +IN and –IN of the ADS8325 is VREF. See Figure 3 for a further explanation of the common-mode voltage range for differential inputs.FIGURE 1. Differential Input Mode of the ADS8325.
ADS8325
SBAS226
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CHANGE IN GAIN vs COMMON-MODE VOLTAGE60Common Voltage Range (V)1VDD = 5V0.50–0.3Delta Relative to VCM = 0V (LSBS)50403020100VDD = 5VVREF = 4V–122.534VREF (V)4.856–10–0.4–0.3–0.2–0.10.00.10.20.30.40.50.60.7VCM (V)FIGURE 3. +IN Analog Input: Common-Mode Voltage Range
vs VREF.Care must be taken regarding the absolute analog inputvoltage. To maintain the linearity of the converter, the –INinput should not drop below GND – 0.3V or exceedGND + 0.5V. The +IN input should always remain within therange of GND – 0.3V to VDD + 0.3V, or –IN to –IN + VREF,whichever limit is reached first. Outside of these ranges, theconverter’s linearity may not meet specifications.
To minimize noise, low bandwidth input signals with low-pass filters should be used. In each case, care should betaken to ensure that the output impedance of the sourcesdriving the +IN and –IN inputs are matched. Often, a smallcapacitor (20pF) between the positive and negative inputshelps to match their impedance. To obtain maximum perfor-mance from the ADS8325, the input circuit from Figure 4 isrecommended.
FIGURE 5. Change in Gain vs Common-Mode Voltage.
CHANGE IN UPO vs COMMON-MODE VOLTAGE30Delta Relative to VCM = 0V (LSBS)20VDD = 5VVREF = 4V100–10–20–0.4–0.3–0.2–0.10.00.10.20.30.40.50.60.7VCM (V)FIGURE 6. Change in Unipolar Offset vs Common-Mode
Voltage.
50ΩOPA340100pF+IN20Ω20pFOPA34050Ω+IN100pF20Ω20pFADS83251nFADS8325–IN20Ω20pFOPA34050Ω–IN100pF20Ω20pFSingle-EndedDifferentialFIGURE 4. Single-Ended and Differential Methods of Interfacing the ADS8325.
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ADS8325
SBAS226
REFERENCE INPUT
The external reference sets the analog input range. TheADS8325 will operate with a reference in the range of 2.5Vto VDD. There are several important implications to this.As the reference voltage is reduced, the analog voltageweight of each digital output code is reduced. This is oftenreferred to as the Least Significant Bit (LSB) size and is equalto the reference voltage divided by 65,536. This means thatany offset or gain error inherent in the A/D converter willappear to increase, in terms of LSB size, as the referencevoltage is reduced. For a reference voltage of 2.5V, the valueof LSB is 38.15µV, and for reference voltage of 5V, the LSBis 76.3µV.
The noise inherent in the converter will also appear toincrease with lower LSB size. With a 5V reference, theinternal noise of the converter typically contributes only1.5LSBs peak-to-peak of potential error to the output code.When the external reference is 2.5V, the potential errorcontribution from the internal noise will be 2 times larger(3LSBs). The errors due to the internal noise are Gaussianin nature and can be reduced by averaging consecutiveconversion results.
For more information regarding noise, consult the typicalcharacteristic “Peak-to-Peak Noise vs Reference Voltage.”Note that the Effective Number Of Bits (ENOB) figure iscalculated based on the converter’s signal-to-(noise + distor-tion) ratio with a 1kHz, 0dB input signal. SINAD is related toENOB as follows:
SINAD = 6.02 • ENOB + 1.76
As the difference between the power-supply voltage and refer-ence voltage increases, the gain and offset performance of theconverter will decrease. Figure 7 shows the typical change ingain and offset as a function of the difference between thepower-supply voltage and reference voltage. For the combina-tion of VDD = 2.7V and VREF = 2.5V, or VDD = 5V and VREF = 5V,offset and gain error will be minimal. The most dramaticdifference in offset can be seen when VDD = 5V and VREF = 2.5V.
With lower reference voltages, extra care should be taken toprovide a clean layout including adequate bypassing, a cleanpower supply, a low-noise reference, and a low-noise inputsignal. Due to the lower LSB size, the converter will also bemore sensitive to external sources of error, such as nearbydigital signals and electromagnetic interference.
The equivalent input circuit for the reference voltage ispresented in the Figure 8. The 5kΩ resistor presents aconstant load during the conversion process. At the sametime, an equivalent capacitor of 20pF is switched. To obtainoptimum performance from the ADS8325, special care mustbe taken in designing the interface circuit to the referenceinput pin. To ensure a stable reference voltage, a 47µFtantalum capacitor with low ESR should be connected asclose as possible to the input pin. If a high output impedancereference source is used, an additional operational amplifierwith a current limiting resistor must be placed in front of thecapacitors.
ADS832520pF100ΩOPA34047µFVREF5kΩFIGURE 8. Input Reference Circuit and its Interface.When the ADS8325 is in power-down mode, the input resis-tance of the reference pin will have a value of 5GΩ. Since theinput capacitors must be recharged before the next conversionstarts, an operational amplifier with good dynamic character-istics must be used to buffer the reference input.
NOISE
The transition noise of the ADS8325 itself is extremely low(see Figures 9 and 10); it is much lower than competing A/Dconverters. These histograms were generated by applying alow-noise DC input and initiating 5000 conversions. The digitaloutput of the A/D converter will vary in output code due to theinternal noise of the ADS8325. This is true for all 16-bit, SAR-type A/D converters. Using a histogram to plot the outputcodes, the distribution should appear bell-shapedwith thepeak of the bell curve representing the nominal code for theinput value. The ±1σ, ±2σ, and ±3σ distributions will representthe 68.3%, 95.5%, and 99.7%, respectively, of all codes. Thetransition noise can be calculated by dividing the number ofcodes measured by 6 and this will yield the ±3σ distribution, or99.7%, of all codes. Statistically, up to three codes could falloutside the distribution when executing 1000 conversions. TheADS8325, with < 3 output codes for the ±3σ distribution, willyield a < ±0.5LSBs of transition noise. Remember, to achievethis low-noise performance, the peak-to-peak noise of theinput signal and reference must be < 50µV.
CHANGE IN OFFSET AND GAIN vsSUPPLY/REFERENCE DIFFERENTIAL3.02.52.0Delta (mV)1.51.0OffsetGain0.50–0.500.250.500.751.001.251.501.752.002.252.502.75 VDD to VREF (V)FIGURE 7. Change in Offset and Gain versus the Difference
between Power-Supply and Reference Voltage.
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4005VDD = 5.0VVREF = 5.0VDIGITAL INTERFACE
SIGNAL LEVELS
The ADS8325 has a wide range of power-supply voltage.The A/D converter, as well as the digital interface circuit, isdesigned to accept and operate from 2.7V up to 5.5V. Thisvoltage range will accommodate different logic levels.When the ADS8325’s power-supply voltage is in the range of4.5V to 5.5V (5V logic level), the ADS8325 can be connecteddirectly to another 5V CMOS integrated circuit.
51907FFD7FFE7FFFCode476080008001Another possibility is that the ADS8325’s power-supply volt-age is in the range of 2.7V to 3.6V. The ADS8325 can beconnected directly to another 3.3V LVCMOS integrated cir-cuit.
FIGURE 9. 5000 Conversion Histogram of a DC Input.
SERIAL INTERFACE
The ADS8325 communicates with microprocessors and otherdigital systems via a synchronous 3-wire serial interface, asillustrated in the Timing Diagram and Timing Characteristicstable. The DCLOCK signal synchronizes the data transferwith each bit being transmitted on the falling edge of DCLOCK.Most receiving systems will capture the bitstream on therising edge of DCLOCK. However, if the minimum hold timefor DOUT is acceptable, the system can use the falling edgeof DCLOCK to capture each bit.
A falling CS signal initiates the conversion and data transfer.The first 4.5 to 5.0 clock periods of the conversion cycle areused to sample the input signal. After the fifth falling DCLOCKedge, DOUT is enabled and will output a LOW value for oneclock period. For the next 16 DCLOCK periods, DOUT willoutput the conversion result, most significant bit first. Afterthe least significant bit (B0) has been output, subsequentclocks will repeat the output data, but in a least significant bitfirst format.
After the most significant bit (B15) has been repeated, DOUTwill tri-state. Subsequent clocks will have no effect on theconverter. A new conversion is initiated only when CS hasbeen taken HIGH and returned LOW.
VDD = 2.7VVREF = 2.5V3499649907FFD7FFE7FFFCode6837980008001FIGURE 10. 5000 Conversion Histogram of a DC Input.
AVERAGING
The noise of the A/D converter can be compensated byaveraging the digital codes. By averaging conversion results,transition noise will be reduced by a factor of 1/n, where nis the number of averages. For example, averaging fourconversion results will reduce the transition noise from±0.5LSB to ±0.25LSB. Averaging should only be used forinput signals with frequencies near DC.
For AC signals, a digital filter can be used to low-pass filterand decimate the output codes. This works in a similarmanner to averaging; for every decimation by 2, the signal-to-noise ratio will improve 3dB.
DATA FORMAT
The output data from the ADS8325 is in Straight Binaryformat (see Figure 11). This figure represents the idealoutput code for a given input voltage and does not includethe effects of offset, gain error, or noise.
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Straight Binary1111 1111 1111 11111111 1111 1111 11111111 1111 1111 1111655356553465533Digital Output Code1000 0000 0000 00011000 0000 0000 00000111 1111 1111 11113276932768327670000 0000 0000 00100000 0000 0000 00010000 0000 0000 0000210VZ = VCM = 0V38.15µV76.29µV152.58µV16-BITZero CodeMidscale CodeFull-Scale Code2.499962V2.500038VVFS = VCM + VREF = 5VVFS – 1LSB = 4.999924V4.999847V1LSB = 76.29µVVCM = 0VVREF = 5VVMS = VCM + VREF/2 = 2.5VUnipolar Analog Input VoltageStraight Binary OutputVZ = 0000HVMS = 8000HVFS = 7FFFHUnipolar Analog InputVCODE = VCMVCODE = VCM + VREF/2VCODE = (VCM + VREF) – 1LSBFIGURE 11. Ideal Conversion Characteristics (Condition: VCM = 0V, VREF = 5V).
POWER DISSIPATION
The architecture of the converter, the semiconductor fabrica-tion process, and a careful design, allow the ADS8325 toconvert at up to a 100kHz rate while requiring very littlepower. However, for the absolute lowest power dissipation,there are several things to keep in mind.
The power dissipation of the ADS8325 scales directly withconversion rate. Therefore, the first step to achieving thelowest power dissipation is to find the lowest conversion ratethat will satisfy the requirements of the system.
In addition, the ADS8325 is in power-down mode under twoconditions: when the conversion is complete and whenever CSis HIGH (see Timing Diagram). Ideally, each conversion shouldoccur as quickly as possible, preferably at a 2.4MHz clock rate.This way, the converter spends the longest possible time in thepower-down mode. This is very important as the converter not
only uses power on each DCLOCK transition (as is typical fordigital CMOS components), but also uses some current for theanalog circuitry, such as the comparator. The analog sectiondissipates power continuously until the power-down mode isentered.
See Figures 12 and 13 for the current consumption of theADS8325 versus sample rate. For these graphs, the con-verter is clocked at 2.4MHz regardless of the sample rate.CS is held HIGH during the remaining sample period.There is an important distinction between the power-downmode that is entered after a conversion is complete and thefull power-down mode that is enabled when CS is HIGH. CSLOW will shutdown only the analog section. The digitalsection is completely shutdown only when CS is HIGH.Thus, if CS is left LOW at the end of a conversion, and theconverter is continually clocked, the power consumption willnot be as low as when CS is HIGH.
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POWER SUPPLY AND REFERENCECURRENT vs SAMPLE RATE1000TA = 25°CVDD = 5.0VVREF = 5.0VFCLK = 2.4MHzIDDLAYOUT
For optimum performance, care should be taken with thephysical layout of the ADS8325 circuitry. This will be particularlytrue if the reference voltage is low and/or the conversion rate ishigh. At a 100kHz conversion rate, the ADS8325 makes a bitdecision every 416ns. That is, for each subsequent bit decision,the digital output must be updated with the results of the last bitdecision, the capacitor array appropriately switched and charged,and the input to the comparator settled to a 16-bit level all withinone clock cycle.
The basic SAR architecture is sensitive to spikes on the powersupply, reference, and ground connections that occur just priorto latching the comparator output. Thus, during any singleconversion for an n-bit SAR converter, there are n “windows” inwhich large external transient voltages can easily affect theconversion result. Such spikes might originate from switchingpower supplies, digital logic, and high-power devices, to namea few. This particular source of error can be very difficult to trackdown if the glitch is almost synchronous to the converter’sDCLOCK signal as the phase difference between the twochanges with time and temperature, causing sporadicmisoperation.
With this in mind, power to the ADS8325 should be clean andwell bypassed. A 0.1µF ceramic bypass capacitor should beplaced as close as possible to the ADS8325 package. Inaddition, a 1µF to 10µF capacitor and a 5Ω or 10Ω seriesresistor may be used to low-pass filter a noisy supply.The reference should be similarly bypassed with a 47µF capaci-tor. Again, a series resistor and large capacitor can be used tolow-pass filter the reference voltage. If the reference voltageoriginates from an op amp, make sure that the op amp candrive the bypass capacitor without oscillation (the series resistorcan help in this case). Keep in mind that while the ADS8325draws very little current from the reference on average, thereare still instantaneous current demands placed on the externalinput and reference circuitry.
Texas Instrument’s OPA627 op amp provides optimum perfor-mance for buffering both the signal and reference inputs. Forlow-cost, low-voltage, single-supply applications, the OPA2350or OPA2340 dual op amps are recommended.
Also, keep in mind that the ADS8325 offers no inherent rejectionof noise or voltage variation in regards to the reference input.This is of particular concern when the reference input is tied tothe power supply. Any noise and ripple from the supply willappear directly in the digital results. While high-frequency noisecan be filtered out as described in the previous paragraph,voltage variation due to the line frequency (50Hz or 60Hz) canbe difficult to remove.
The GND pin on the ADS8325 should be placed on a cleanground point. In many cases, this will be the “analog” ground.Avoid connecting the GND pin too close to the grounding pointfor a microprocessor, microcontroller, or digital signal proces-sor. If needed, run a ground trace directly from the converter tothe power-supply connection point. The ideal layout will includean analog ground plane for the converter and associated analogcircuitry.
Current (µA)10010IREF110Sample Rate (kHz)100FIGURE 12. Power-Supply and Reference Current vs Sample
Rate at VDD = 5V.
POWER SUPPLY AND REFERENCECURRENT vs SAMPLE RATE1000TA = 25°CVDD = 2.7VVREF = 2.5VFCLK = 2.4MHzIDDCurrent (µA)10010IREF110Sample Rate (kHz)100FIGURE 13. Power-Supply and Reference Current vs Sample
Rate at VDD = 2.7V.
SHORT CYCLING
Another way to save power is to utilize the CS signal to shortcycle the conversion. Due to the ADS8325 placing the latestdata bit on the DOUT line as it is generated, the converter caneasily be short cycled. This term means that the conversioncan be terminated at any time. For example, if only 14 bits ofthe conversion result are needed, then the conversion can beterminated (by pulling CS HIGH ) after the 14th bit has beenclocked out.
This technique can be used to lower the power dissipation (orto increase the conversion rate) in those applications wherean analog signal is being monitored until some conditionbecomes true. For example, if the signal is outside a prede-termined range, the full 16-bit conversion result may not beneeded. If so, the conversion can be terminated after the firstn bits, where n might be as low as 3 or 4. This results in lowerpower dissipation in both the converter and the rest of thesystem as they spend more time in power-down mode.
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APPLICATION CIRCUITS
Figure 14 shows a basic data acquisition system. TheADS8325 input range is connected to 2.5V or 4.096V. The5Ω resistor and 1µF to 10µF capacitor filters the microcon-
troller “noise” on the supply, as well as any high-frequencynoise from the supply itself. The exact values should bepicked such that the filter provides adequate rejection ofnoise. Operational amplifiers and voltage reference are con-nected to analog power supply, AVDD.
DVDD2.7V to 3.6V0.1µFAVDD2.7V to 5VREF3025IN0.47µFOUTGND100ΩOPA34047µFADS8325DSP50ΩOPA340VCM + (0V to 2.5V)100pF1nF50ΩOPA340VCM100pF–IN+INCSDOUTDCLOCKGNDGNDTMS320C6xxorTMS320C5xxorTMS320C2xxREFVDD0.1µF+10µF5Ω+10µFDVDD4.5V to 5.5V0.1µFAVDD4.3V to 5.5VREF3040IN0.47µFOUTGND100ΩOPA34047µFADS8325MicrocontrollerorDSP+IN100pFCSDOUTDCLOCK–INGNDGNDREFVDD0.1µF+10µF5Ω+10µF50ΩOPA3400V to 4.096VFIGURE 14. Two Examples of a Basic Data Acquisition System.
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PACKAGE DRAWING
MPDS028B – JUNE 1997 – REVISED SEPTEMBER 2001DGK (R-PDSO-G8) 0,380,2585PLASTIC SMALL-OUTLINE PACKAGE0,650,08M0,15 NOM3,052,954,984,78Gage Plane0,2513,052,9540°–6°0,690,41Seating Plane1,07 MAX0,150,050,104073329/C 08/01NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion.Falls within JEDEC MO-18718
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