专利名称：Process for Improving the Reliability of
Interconnect Structures and ResultingStructure
发明人：Hsien-Wei Chen,Jian-Hong Lin,Tzu-Li Lee申请号：US12879770申请日：20100910
公开号：US20100327456A1公开日：20101230
专利附图：
摘要：An interconnect structure of an integrated circuit having improved reliability anda method for forming the same are provided. The method includes providing a substrate,
forming a dielectric layer overlying the substrate, performing a first shrinking process,wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductivefeature in the dielectric layer after the step of performing the first shrinking process, andperforming a second shrinking process after the step of forming the conductive feature,wherein the dielectric layer substantially shrinks and has a second shrinkage rate.
申请人：Hsien-Wei Chen,Jian-Hong Lin,Tzu-Li Lee
地址：Sinying City TW,Yunlin TW,Yunlin TW
国籍：TW,TW,TW
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