Process for improving the reliability of interconn

专利名称：Process for improving the reliability of

interconnect structures and resultingstructure

发明人：Hsien-Wei Chen,Jian-Hong Lin,Tzu-Li Lee申请号：US11487741申请日：20060717

公开号：US20080014741A1公开日：20080117

专利附图：

摘要：An interconnect structure of an integrated circuit having improved reliability anda method for forming the same are provided. The method includes providing a substrate,

forming a dielectric layer overlying the substrate, performing a first shrinking process,wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductivefeature in the dielectric layer after the step of performing the first shrinking process, andperforming a second shrinking process after the step of forming the conductive feature,wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

申请人：Hsien-Wei Chen,Jian-Hong Lin,Tzu-Li Lee

地址：Sinying City TW,Yunlin TW,Yunlin TW

国籍：TW,TW,TW

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