64x 汇编指令 有关DSP

TMS320C64x 指令集 指令 语法 ABS ABS (.unit) src2, dst .unit = .L1 or .L2 ABS2 ABS2 (.unit) src2, dst .unit = .L1 or .L2 ADD ADDAB ADD(.unit) src1, src2, dst .unit= .D1, .D2, .L1, .L2, .S1, .S2 ADDAB(.unit) src2, src1,dst .unit = .D1 or .D2 描述 The absolute value of src2 is placed in dst. The absolute values of the upper and lower halves of the src2 operand are placed in the upper and lower halves of the dst. src2 is added to src1. The result is placed in dst. ADDAD ADDAH ADDAW ADDK For the C64x and C64x+ CPU, src1 is added to src2 using the byte addressing mode specified for src2. The addition defaults to linear mode. However, if src2 is one of A4-A7 or B4-B7, the mode can be changed to circular mode by writing the appropriate value to the AMR . The result is placed in dst. ADDAD(.unit) src2, src1,dst src1 is added to src2 using the doubleword .unit = . D1 or .D2 addressing mode specified for src2. The addition defaults to linear mode. However, if src2 is one of A4-A7 or B4-B7, the mode can be changed to circular mode by writing the appropri-ate value to the AMR . src1 is left shifted by 3 due to doubleword data sizes. The result is placed in dst. ADDAH(.unit) src2, src1, dst For the C64x and C64x+ CPU, src1 is added .unit = .D1 or .D2 to src2 using the halfword addressing mode specified for src2. The addition defaults to linear mode.However, if src2 is one of A4-A7 or B4-B7, the mode can be changed to circular mode by writing the appropriate value to the AMR . If circular addressing is enabled, src1 is left shifted by 1. The result is placed in dst. ADDAW(.unit) src2, src1,dst For the C64x and C64x+ CPU, src1 is added .unit = .D1 or .D2 to src2 using the word addressing mode specified for src2. The addition defaults to linear mode. However, if src2 is one of A4-A7 or B4-B7, the mode can be changed to circular mode by writing the appropriate value to the AMR . If circular addressing is enabled, src1 is left shifted by 2. The result is placed in dst. ADDK(.unit) cst, dst A 16-bit signed constant, cst16, is added to .unit = .S1 or .S2 the dst register specified. The result is placed in dst. ADDKPC ADDKPC(.unit)src1,dst,src2 .unit = .S2 ADDU ADD2 ADDU(.unit) src1, src2, dst .unit = .L1 or .L2 ADD2(.unit) src1, src2, dst .unit= .S1, .S2, .L1, .L2, .D1, .D2 ADD4 ADD4(.unit) src1, src2, dst .unit = .L1 or .L2 AND ANDN AVG2 (.unit) src1, src2, dst .unit= .L1, .L2, .S1, .S2, .D1, .D2 ANDN (.unit) src1, src2, dst .unit=.L1,.L2,S1, .S2, .D1, .D2 AVG2(.unit) src1, src2, dst .unit = .M1 or .M2 AVGU4 AVGU4(.unit) src1, src2, dst .unit = .M1 or .M2 B displacement B displacement(.unit) label .unit = .S1 or .S2 B register B register (.unit) src2 .unit = .S2 A 7-bit signed constant, src1, is shifted 2 bits to the left, then added to theaddress of the first instruction of the fetch packet that contains the ADDKPC instruction (PCE1). The result is placed in dst. The 3-bit unsigned constant, src2, specifies the number of NOP cycles to insert after the current instruction. This instruction helps reduce the number of instructions needed to set up the return address for a function call. src2 is added to src1. The result is placed in dst The upper and lower halves of the src1 operand are added to the upper and lower halves of the src2 operand. The values in src1 and src2 are treated as signed, packed 16-bit data and the results are written in signed, packed 16-bit format into dst. Performs 2s-complement addition between packed 8-bit quantities. The values in src1 and src2 are treated as packed 8-bit data and the results are written into dst in a packed 8-bit format. Performs a bitwise AND operation between src1 and src2. The result is placed in dst. The scst5 operands are sign extended to 32 bits. Performs a bitwise logical AND operation between src1 and the bitwise logical inverse of src2. The result is placed in dst. Performs an averaging operation on packed 16-bit data. For each pair of signed 16-bit values found in src1 and src2, AVG2 calculates the average of the two values and returns a signed 16-bit quantity in the corresponding position in the dst. Performs an averaging operation on packed 8-bit data. The values in src1 and src2 are treated as unsigned, packed 8-bit data and the results are written in unsigned, packed 8-bit format. For each unsigned, packed 8-bit value found in src1 and src2, AVGU4 calculates the average of the two values and returns an unsigned, 8-bit quantity in the corresponding positions in the dst. A 21-bit signed constant, cst21, is shifted left by 2 bits and is added to the address of the first instruction of the fetch packet that contains the branch instruction. The result is placed in the program fetch counter (PFC). The assembler/linker automatically computes the correct value for cst21 by the following formula: cst21 = (label - PCE1) >> 2 If two branches are in the same execute packet and both are taken, behavior is undefined. src2 is placed in the program fetch counter (PFC). B IRP B IRP(.unit) IRP .unit = .S2 B NRP(.unit) NRP .unit = .S2 BDEC(.unit) src, dst .unit = .S1 or .S2 B NRP BDEC BITC4 BITC4(.unit) src2, dst .unit = .M1 or .M2 BITR BITR(.unit) src2, dst .unit = .M1 or .M2 BNOP displace BNOP displace (.unit) src2, src1 .unit = .S1 or .S2 BNOP register BNOP register(.unit) src2, src1 .unit = .S2 BPOS BPOS (.unit) src, dst .unit = .S1 or .S2 IRP is placed in the program fetch counter (PFC). This instruction also moves the PGIE bit value to the GIE bit. The PGIE bit is unchanged. NRP is placed in the program fetch counter (PFC). This instruction also sets the NMIE bit. The PGIE bit is unchanged. If the predication and decrement register (dst) is positive (greater than or equal to 0), the BDEC instruction performs a relative branch and decrements dst by 1. The instruction performs the relative branch using a 10-bit signed constant, scst10, in src. The constant is shifted 2 bits to the left, then added to the address of the first instruction of the fetch packet that contains the BDEC instruction (PCE1). The result is placed in the program fetch counter (PFC). Performs a bit-count operation on 8-bit quantities. The value in src2 is treated as packed 8-bit data, and the result is written in packed 8-bit format. For each of the 8-bit quantities in src2, the count of the number of 1 bits in that value is written to the corresponding position in dst. Implements a bit-reversal function that reverses the order of bits in a 32-bit word. This means that bit 0 of the source becomes bit 31 of the result, bit 1 of the source becomes bit 30 of the result, bit 2 becomes bit 29, and so on. The constant displacement form of the BNOP instruction performs a relative branch with NOP instructions. The instruction performs the relative branch using the 12-bit signed constant specified by src2. The register form of the BNOP instruction performs an absolute branch with NOP instructions. The register specified in src2 is placed in the program fetch counter (PFC). If the predication register (dst) is positive (greater than or equal to 0), the BPOS instruction performs a relative branch. If dst is negative, the BPOS instruction takes no other action. CLR CLR(.unit) src2, csta, cstb, dst .unit = .S1 or .S2 CMPEQ CMPEQ2 CMPEQ(.unit) src1, src2, dst .unit = .L1 or .L2 CMPEQ2(.unit) src1, src2, dst .unit = .S1 or .S2 CMPEQ4 CMPEQ4(.unit) src1, src2, dst .unit = .S1 or .S2 CMPGT CMPGT2 CMPGT(.unit) src1, src2, dst .unit = .L1 or .L2 CMPGT2 (.unit) src1, src2, dst .unit = .S1 or .S2 CMPGTU CMPGTU (.unit) src1, src2, dst .unit = .L1 or .L2 For cstb > csta, the field in src2 as specified by csta to cstb is cleared to all 0s in dst. The csta and cstb operands may be specified as constants or in the 10 LSBs of the src1 register, with cstb being bits 0-4 (src14.0)and csta being bits 5-9 (src19..5 ).csta is the LSB of the field and cstb is the MSB of the field. In other words, csta and cstb represent the beginning and ending bits, respectively, of the field to be cleared to all 0s in dst. The LSB location of src2 is bit 0 and the MSB location of src2 is bit 31. Compares src1 to src2. If src1 equals src2, then 1 is written to dst; otherwise, 0 is written to dst. Performs equality comparisons on packed 16-bit data. Each 16-bit value in src1 is compared against the corresponding 16-bit value in src2, returning either a 1 if equal or a 0 if not equal. The equality results are packed into the two least-significant bits of dst. The result for the lower pair of values is placed in bit 0, and the results for the upper pair of values are placed in bit 1. The remaining bits of dst are cleared to 0. Performs equality comparisons on packed 8-bit data. Each 8-bit value in src1 is compared against the corresponding 8-bit value in src2, returning either a 1 if equal or a 0 if not equal. The equality comparison results are packed into the four least-significant bits of dst. Performs a signed comparison of src1 to src2. If src1 is greater than src2, then a 1 is written to dst; otherwise, a 0 is written to dst. Performs comparisons for greater than values on signed, packed 16-bit data. Each signed 16-bit value in src1 is compared against the corresponding signed 16-bit value in src2, returning a 1 if src1 is greater than src2 or returning a 0 if it is not greater. The comparison results are packed into the two least-significant bits of dst. The result for the lower pair of values is placed in bit 0,and the results for the upper pair of values are placed in bit 1. The remaining bits of dst are cleared to 0. Performs an unsigned comparison of src1 to src2. If src1 is greater than src2,then a 1 is written to dst; otherwise, a 0 is written to dst. Only the four LSBs are valid in the 5-bit dst field when the ucst4 operand is used. If the MSB of the dst field is nonzero, the result is invalid. CMPGTU4 CMPGTU4(.unit) src1,src2, dst .unit = .S1 or .S2 CMPLT CMPLT2 CMPLTU CMPLTU4 DEAL DOTP2 Performs comparisons for greater than values on packed 8-bit data. Each unsigned 8-bit value in src1 is compared against the corresponding unsigned 8-bit value in src2, returning a 1 if the byte in src1 is greater than the corre-sponding byte in src2 or a 0 if is not greater. The comparison results are packed into the four least-significant bits of dst. CMPLT (.unit) src1, src2, dst Performs a signed comparison of src1 to src2. .unit = .L1 or .L2 If src1 is less than src2, then 1 is written to dst; otherwise, 0 is written to dst. CMPLT2 (.unit) src2, src1, The CMPLT2 instruction is a dst pseudo-operation used to perform .unit = .S1 or .S2 less-thancomparisons on signed, packed 16-bit data. Each signed 16-bit value in src2 is compared against the corresponding signed 16-bit value in src1, returning a 1 if src2 is less than src1 or returning a 0 if it is not less than. The comparison results are packed into the two least-significant bits of dst. The result for thelower pair of values is placed in bit 0, and the results for the upper pair of values are placed in bit 1. The remaining bits of dst are cleared to 0. The assembler uses the operation CMPGT2 (.unit) src1, src2, dst to perform this task. CMPLTU (.unit) src1, src2, Performs an unsigned comparison of src1 to dst src2. If src1 is less than src2, then 1 is written .unit = .L1 or .L2 to dst; otherwise, 0 is written to dst. CMPLTU4(.unit) src2, src1, The CMPLTU4 instruction is a dst pseudo-operation that performs less-than .unit = .S1 or .S2 comparisons on packed 8-bit data. Each unsigned 8-bit value in src2 is comparedagainst the corresponding unsigned 8-bit value in src1, returning a 1 if the byte in src2 is less than the corresponding byte in src1 or a 0 it if is not less than. The comparison results are packed into the four least-significant bits of dst. DEAL (.unit) src2, dst Performs a deinterleave and pack operation .unit = .M1 or .M2 on the bits in src2. The odd and even bits of src2 are extracted into two separate, 16-bit quantities. These 16-bit quantities are then packed such that the even bits are placed in the lower halfword, and the odd bits are placed in the upper halfword. DOTP2 (.unit) src1, src2, dst Returns the dot-product between two pairs of .unit = .M1 or .M2 signed, packed 16-bit values.The values in src1 and src2 are treated as signed, packed 16-bit quantities.The signed result is written either to a single 32-bit register, or sign-extended into a 64-bit register pair. DOTPN2 DOTPN2 (.unit) src1, src2, dst .unit = .M1 or .M2 DOTPNRSU2 DOTPNRSU2(.unit)src1,src2, dst .unit = .M1 or .M2 DOTPNRUS2 DOTPNRUS2(.unit)src2,src1,dst .unit = .M1 or .M2 DOTPRSU2 DOTPRSU2(.unit)src1,src2, dst .unit = .M1 or .M2 DOTPRUS2 DOTPRUS2 (.unit) src2, src1, dst .unit = .M1 or .M2 DOTPSU4 DOTPSU4(.unit)src1,src2,dst.unit = .M1 or .M2 Returns the dot-product between two pairs of signed, packed 16-bit values where the second product is negated. The values in src1 and src2 are treated as signed, packed 16-bit quantities. The signed result is written to a single 32-bit register. Returns the dot-product between two pairs of packed 16-bit values, where the second product is negated. This instruction takes the result of the dot-product and performs an additional round and shift step. The values in src1 are treated as signed, packed 16-bit quantities; whereas, the values in src2 are treated as unsigned, packed 16-bit quantities. The results are written to dst. The DOTPNRUS2 pseudo-operation performs the dot-product between two pairs of packed 16-bit values, where the second product is negated. This instruction takes the result of the dot-product and performs an additional round and shift step. The values in src1 are treated as signed, packed 16-bit quantities; whereas, the values in src2 are treated as unsigned, packed 16-bit quantities. The results are written to dst. The assembler uses the DOTPNRSU2 src1, src2, dst instruction to perform this task. Returns the dot-product between two pairs of packed 16-bit values. This instruction takes the result of the dot-product and performs an additional round and shift step. The values in src1 are treated as signed packed 16-bit quantities; whereas, the values in src2 are treated as unsigned packed 16-bit quantities. The results are written to dst. The DOTPRUS2 pseudo-operation returns the dot-product between two pairs of packed 16-bit values. This instruction takes the result of the dot-product,and performs an additional round and shift step. The values in src1 are treated as signed packed 16-bit quantities; whereas, the values in src2 are treated as unsigned packed 16-bit quantities. The results are written to dst. The assembler uses the DOTPRSU2 (.unit) src1, src2, dst instruction to perform this task. Returns the dot-product between four sets of packed 8-bit values. The values in src1 are treated as signed packed 8-bit quantities; whereas, the values in src2 are treated as unsigned 8-bit packed data. The signed result is written intodst. DOTPUS4 DOTPUS4(.unit) src2, src1, dst .unit = .M1 or .M2 DOTPU4 EXT EXTU GMPY4 IDLE The DOTPUS4 pseudo-operation returns the dot-product between four sets of packed 8-bit values. The values in src1 are treated as signed packed 8-bit quantities; whereas, the values in src2 are treated as unsigned 8-bit packed data. The signed result is written into dst. The assembler uses the DOTPSU4 (.unit) src1, src2, dst instruction to perform this task. DOTPU4 (.unit) src1, src2, Returns the dot-product between four sets of dst packed 8-bit values. The values in both src1 .unit = .M1 or .M2 and src2 are treated as unsigned, 8-bit packed data. The unsigned result is written into dst. EXT (.unit) src2, csta, cstb, The field in src2, specified by csta and cstb, is dst extracted and sign-extended to 32 bits. The .unit = .S1 or .S2 extract is performed by a shift left followed by a signed shift right. csta and cstb are the shift left amount and shift right amount, respectively. This can be thought of in terms of the LSB and MSB of the field to be extracted. Then csta = 31 - MSB of the field and cstb = csta + LSB of the field. The shift left and shift right amounts may also be specified as the ten LSBs of the src1 register with cstb being bits 0?4 and csta bits 5-9. In the example below, csta is 12 and cstb is 11 + 12 = 23. Only the ten LSBs are valid for the register version of the instruction. If any of the 22 MSBs are non-zero, the result is invalid. EXTU(.unit)src2,csta,cstb, The field in src2, specified by csta and cstb, is dst extracted and zero extended to 32 bits. The .unit = .S1 or .S2 extract is performed by a shift left followed by an unsigned shift right. csta and cstb are the amounts to shift left and shift right, respectively. This can be thought of in terms of the LSB and MSB of the field to be extracted.Then csta = 31 - MSB of the field and cstb = csta + LSB of the field. The shift left and shift right amounts may also be specified as the ten LSBs of the src1 register with cstb being bits 0-4 and csta bits 5-9. In the example below, csta is 12 and cstb is 11 + 12 = 23. Only the ten LSBs are valid for the register version of the instruction. If any of the 22 MSBs are non-zero, the result is invalid. GMPY4 (.unit) src1, src2, dst Performs the Galois field multiply on four .unit = .M1 or .M2 values in src1 with four parallel values in src2. The four products are packed into dst. The values in both src1 and src2 are treated as unsigned, 8-bit packed data. IDLE Performs an infinite multicycle NOP that .unit = none terminates upon servicing an interrupt, or a branch occurs due to an IDLE instruction being in the delay slots of a branch. LDB memory LDB (.unit) *+baseR[ucst5], dst .unit = .D1 or .D2 LDB LDB(.unit) memory(15-bit *+B14/B15[ucst15], dst offset) .unit = .D2 LDBU LDBU(.unit)*+baseR[offsetmemory R], dst .unit = .D1 or .D2 LDBU LDBU(.unit)*+B14/B15[ucstmemory 15], dst (15-bit offset) .unit = .D2 LDDW LDDW(.unit)*+baseR[offsetR], dst_o:dst_e .unit = .D1 or .D2 LDH memory LDH (.unit) *+baseR[ucst5], dst.unit = .D1 or .D2 LDH memory LDH(.unit)*+B14/B15[ucst1(15-bit offset) 5], dst .unit = .D2 LDHU LDHU (.unit) memory *+baseR[ucst5], dst .unit = .D1 or .D2 LDHU LDHU(.unit)*+B14/B15[ucstmemory 15], ds (15-bit offset) .unit = .D2 LDNDW LDNDW(.unit)*+baseR[offsetR], dst .unit = .D1 or .D2 LDNW LDNW(.unit)*+baseR[offsetR], dst .unit = .D1 or .D2 LDW memory LDW (.unit) *+baseR[offsetR], dst .unit = .D1 or .D2 LDW memory LDW(.unit)*+B14/B15[ucst1(15-bit offset) 5], dst .unit = .D2 Loads a byte from memory to a general-purpose register (dst). Loads a byte from memory to a general-purpose register (dst). Loads a byte from memory to a general-purpose register (dst). Loads a byte from memory to a general-purpose register (dst). Loads a 64-bit quantity from memory into a register pair dst_o:dst_e. Loads a halfword from memory to a general-purpose register (dst). Loads a halfword from memory to a general-purpose register (dst).. Loads a 64-bit quantity from memory into a register pair dst_o:dst_e. Loads a 64-bit quantity from memory into a register pair dst_o:dst_e. Loads a 64-bit quantity from memory into a register pair, dst_o:dst_e. Loads a 32-bit quantity from memory into a 32-bit register, dst. Loads a word from memory to a general-purpose register (dst). Load a word from memory to a general-purpose register (dst). The memoryaddress is formed from a base address register B14 (y = 0) or B15 (y = 1) and an offset, which is a 15-bit unsigned constant (ucst15). The assembler selects this format only when the constant is larger than five bits in magnitude. This instruction operates only on the .D2 unit. The LSB of the src1 operand determines whether to search for a leftmost 1 or 0 in src2. The number of bits to the left of the first 1 or 0 when searching for a 1or 0, respectively, is placed in dst. Performs a maximum operation on signed, packed 16-bit values. For each pairof signed 16-bit values in src1 and src2, MAX2 places the larger value in thecorresponding position in dst. LMBD LMBD (.unit) src1, src2, dst .unit = .L1 or .L2 MAX2 MAX2 (.unit) src1, src2, dst .unit = .L1 or .L2 MAXU4 MAXU4 (.unit) src1, src2, dst .unit = .L1 or .L2 MIN2 MINU4 MPY MPYH MPYHI MPYHIR MPYHL MPYHLU MPYHSLU MPYHSU MPYHU Performs a maximum operation on unsigned, packed 8-bit values. For eachpair of unsigned 8-bit values in src1 and src2, MAXU4 places the larger valuein the corresponding position in dst. MIN2 (.unit) src1, src2, dst Performs a minimum operation on signed, .unit = .L1 or .L2 packed 16-bit values. For each pairof signed 16-bit values in src1 and src2, MIN2 instruction places the smallervalue in the corresponding position in dst. MINU4 (.unit) src1, src2, dst Performs a minimum operation on unsigned, .unit = .L1 or .L2 packed 8-bit values. For eachpair of unsigned 8-bit values in src1 and src2, MINU4 places the smaller valuein the corresponding position in dst. MPY (.unit) src1, src2, dst The src1 operand is multiplied by the src2 .unit = .M1 or .M2 operand. The result is placed in dstThe source operands are signed by default. MPYH (.unit) src1, src2, dst The src1 operand is multiplied by the src2 .unit = .M1 or .M2 operand. The result is placed in dst.The source operands are signed by default. MPYHI(.unit)src1,src2,dst_oPerforms a 16-bit by 32-bit multiply. The :dst_e upper half of src1 is used as a signed16-bit .unit = .M1 or .M2 input. The value in src2 is treated as a signed 32-bit value. The resultis written into the lower 48 bits of a 64-bit register pair, dst_o:dst_e, and signextended to 64 bits. MPYHIR (.unit) src1, src2, Performs a 16-bit by 32-bit multiply. The dst upper half of src1 is treated as a signed 16-bit .unit = .M1 or .M2 input. The value in src2 is treated as a signed 32-bit value. The 14 and then thisproduct is then rounded to a 32-bit result by adding the value 2 sum is right shifted by 15. The lower 32 bits of the result are written into dst. MPYHL (.unit) src1, src2, The src1 operand is multiplied by the src2 dst operand. The result is placed in dstThe source .unit = .M1 or .M2 operands are signed by default. MPYHLU (.unit) src1, src2, The src1 operand is multiplied by the src2 dst operand. The result is placed in dst.The .unit = .M1 or .M2 source operands are unsigned by default. MPYHSLU (.unit) src1, src2, The signed operand src1 is multiplied by the dst.unit = .M1 or .M2 unsigned operand src2. The resultis placed in dst. The S is needed in the mnemonic to specify a signed operandwhen both signed and unsigned operands are used. MPYHSU (.unit) src1, src2, The signed operand src1 is multiplied by the dst unsigned operand src2. The resultis placed in .unit = .M1 or .M2 dst. The S is needed in the mnemonic to specify a signed operandwhen both signed and unsigned operands are used. MPYHU (.unit) src1, src2, The src1 operand is multiplied by the src2 dst operand. The result is placed in dst.The .unit = .M1 or .M2 source operands are unsigned by default. MPYHULS MPYHUS MPYIH MPYIHR MPYIL MPYILR MPYLH MPYLHU MPYHULS (.unit) src1, src2, The unsigned operand src1 is multiplied by dst the signed operand src2. The resultis placed .unit = .M1 or .M2 in dst. The S is needed in the mnemonic to specify a signed operandwhen both signed and unsigned operands are used. MPYHUS (.unit) src1, src2, The unsigned operand src1 is multiplied by dst the signed operand src2. The resultis placed .unit = .M1 or .M2 in dst. The S is needed in the mnemonic to specify a signed operandwhen both signed and unsigned operands are used. MPYIH (.unit) src2, src1, The MPYIH pseudo-operation performs a dst_o:dst_e 16-bit by 32-bit multiply. The uppehalf of .unit = .M1 or .M2 src1 is used as a signed 16-bit input. The value in src2 is treated as asigned 32-bit value. The result is written into the lower 48 bits of a 64-bit registepair, dst_o:dst_e, and sign extended to 64 bits. The assembler uses theMPYHI (.unit) src1, src2, dst_o:dst_e instruction to perform this operation. MPYIHR (.unit) src2, src1, The MPYIHR pseudo-operation performs a dst 16-bit by 32-bit multiply. The upper half of .unit = .M1 or .M2 src1 is treated as a signed 16-bit input. The value in src2 is treated as a signed 32-bit value. The product is then rounded to a 32-bit result 14 and then this sum is right shifted by 15. The lower by adding the value 232 bits of the result are written into dst. The assembler uses the MPYHIR (.unit) src1, src2, dst instruction to perform this operation. MPYIL (.unit) src2, src1, The MPYIL pseudo-operation performs a dst_o:dst_e 16-bit by 32-bit multiply. The lowerhalf of .unit = .M1 or .M2 src1 is used as a signed 16-bit input. The value in src2 is treated as asigned 32-bit value. The result is written into the lower 48 bits of a 64-bit regis-ter pair, dst_o:dst_e, and sign extended to 64 bits. The assembler uses theMPYLI (.unit) src1, src2, dst instruction to perform this operation. MPYILR (.unit) src2, src1, The MPYILR pseudo-operation performs a dst 16-bit by 32-bit multiply. Thelower half of .unit = .M1 or .M2 src1 is used as a signed 16-bit input. The value in src2 is treatedas a signed 32-bit value. The product is then rounded to a 32-bit result by14 and then this sum is right shifted by 15. The lower 32 bits adding the value 2of the result are written into dst. The assembler uses the MPYLIR (.unit) src1, src2, dst instruction to perform this operation. MPYLH (.unit) src1, src2, The src1 operand is multiplied by the src2 dst operand. The result is placed in dst.The .unit = .M1 or .M2 source operands are signed by default. MPYLHU (.unit) src1, src2, The src1 operand is multiplied by the src2 dst.unit = .M1 or .M2 operand. The result is placed in dst.The source operands are unsigned by default. MPYLI MPYLI (.unit) src1, src2, dst_o:dst_e .unit = .M1 or .M2 MPYLIR MPYLIR (.unit) src1, src2, dst .unit = .M1 or .M2 MPYLSHU MPYLSHU (.unit) src1, src2, dst .unit = .M1 or .M2 MPYLUHS (.unit) src1, src2, dst .unit = .M1 or .M2 MPYSU (.unit) src1, src2, dst .unit = .M1 or .M2 MPYLUHS MPYSU MPYSU4 MPYSU4 (.unit) src1, src2, dst_o:dst_e .unit = .M1 or .M2 MPYU MPYU4 MPYU (.unit) src1, src2, dst .unit = .M1 or .M2 MPYU4 (.unit) src1, src2, dst_o:dst_e .unit = .M1 or .M2 MPYUS MPYUS (.unit) src1, src2, dst .unit = .M1 or .M2 Performs a 16-bit by 32-bit multiply. The lower half of src1 is used as a signed16 bit input. The value in src2 is treated as a signed 32-bit value. The resultis written into the lower 48 bits of a 64-bit register pair, dst_o:dst_e, and signextended to 64 bits. Performs a 16-bit by 32-bit multiply. The lower half of src1 is treated as a signed16-bit input. The value in src2 is treated as a signed 32-bit value. The product14 and then this sum is then rounded into a 32-bit result by adding the value 2is right shifted by 15. The lower 32 bits of the result are written into dst. The signed operand src1 is multiplied by the unsigned operand src2. The resultis placed in dst. The S is needed in the mnemonic to specify a signed operandwhen both signed and unsigned operands are used. The unsigned operand src1 is multiplied by the signed operand src2. The resultis placed in dst. The S is needed in the mnemonic to specify a signed operandwhen both signed and unsigned operands are used. The signed operand src1 is multiplied by the unsigned operand src2. The resultis placed in dst. The S is needed in the mnemonic to specify a signed operandwhen both signed and unsigned operands are used. Returns the product between four sets of packed 8-bit values producing foursigned 16-bit results. The four signed 16-bit results are packed into a 64-bitregister pair, dst_o:dst_e. The values in src1 are treated as signed 8-bitpacked quantities; whereas, the values in src2 are treated as unsigned 8-bitpacked data. The src1 operand is multiplied by the src2 operand. The result is placed in dst.The source operands are unsigned by default. Returns the product between four sets of packed 8-bit values producing fourunsigned 16-bit results that are packed into a 64-bit register pair, dst_o:dst_e.The values in both src1 and src2 are treated as unsigned 8-bit packed data. The unsigned operand src1 is multiplied by the signed operand src2. The resultis placed in dst. The S is needed in the mnemonic to specify a signed operandwhen both signed and unsigned operands are used. MPYUS4 MPYUS4 (.unit) src2, src1, dst_o:dst_e .unit = .M1 or .M2 MPY2 MPY2 (.unit) src1, src2, dst_o:dst_e .unit = .M1 or .M2 MV MV (.unit) src2, dst .unit= .L1, .L2, .S1, .S2, .D1, .D2 MVC (.unit) src2, dst .unit = .S2 MVD (.unit) src2, dst .unit = .M1 or .M2 MVK (.unit) cst, dst .unit= .L1, .L2, .S1, .S2, .D1, .D2 MVKH (.unit) cst, dst .unit = .S1 or .S2 MVC MVD MVK MVKH MVKL MVKLH MVKL (.unit) cst, dst .unit = .S1 or .S2 MVKLH (.unit) cst, dst .unit = .S1 or .S2 NEG NEG (.unit) src2, dst .unit = .L1, .L2, .S1, .S2 NOP [count] .unit = none NORM (.unit) src2, dst .unit = .L1 or .L2 NOP NORM The MPYUS4 pseudo-operation returns the product between four sets ofpacked 8-bit values, producing four signed 16-bit results. The four signed16-bit results are packed into a 64-bit register pair, dst_o:dst_e. The values insrc1 are treated as signed 8-bit packed quantities; whereas, the values in src2are treated as unsigned 8-bit packed data. The assembler uses theMPYSU4 (.unit) src1, src2, dst instruction to perform this operation. Performs two 16-bit by 16-bit multiplications between two pairs of signed, packed 16-bit values. The values in src1 and src2 are treated as signed,packed 16-bit quantities. The two 32-bit results are written into a 64-bit registerpair. The MV pseudo-operation moves a value from one register to another. Theassembler will either use the ADD (.unit) 0, src2, dst or the OR (.unit) 0, src2,dst operation to perform this task. For the C64x and C64x+ CPU, the contents of the control fle specified by thecrlo field is moved to the register file specified by the dst field. Moves data from the src2 register to the dst register over 4 cycles. This is doneusing the multiplier path. The constant cst is sign extended and placed in dst. The .S unit form allowsfor a 16-bit signed constant. The 16-bit constant, cst16 , is loaded into the upper 16 bits of dst. The 16 LSBsof dst are unchanged. For the MVKH instruction, the assembler encodes the16 MSBs of a 32-bit constant into the cst16 field of the opcode . The 16-bit constant, cst16, is sign extended and placed in dst he 16-bit constant, cst16 , is loaded into the upper 16 bits of dst. The 16 LSBsof dst are unchanged. For the MVKLHinstruction, the assembler encodes the 16 LSBs of a constant into the cst16field of the opcode. The NEG pseudo-operation negates src2 and places the result in dst. Theassembler uses SUB (.unit) 0, src2, dst to perform this operation. src is encoded as count - 1. For src + 1 cycles, no operation is performed. Themaximum value for count is 9. NOP with no operand is treated like NOP 1 withsrc encoded as 0000. The number of redundant sign bits of src2 is placed in dst. Several examplesare shown in the following diagram. NOT NOT (.unit) src2, dst.unit = .L1, .L2, .S1, .S2 OR PACK2 PACKH2 PACKH4 PACKHL2 PACKLH2 PACKL4 ROTL The NOT pseudo-operation performs a bitwise NOT on the src2 operand andplaces the result in dst. The assembler uses XOR (.unit) -1, src2, dst toperform this operation. OR (.unit) src1, src2, dst Performs a bitwise OR operation between .unit src1 and src2. The result is placedin dst. The =.D1, .D2, .L1, .L2, .S1, .S2 scst5 operands are sign extended to 32 bits. PACK2 (.unit) src1, src2, dst Moves the lower halfwords from src1 and .unit = .L1, .L2, .S1, .S2 src2 and packs them both into dst.The lower halfword of src1 is placed in the upper halfword of dst. The lowerhalfword of src2 is placed in the lower halfword of dst. PACKH2 (.unit) src1, src2, Moves the upper halfwords from src1 and dst src2 and packs them both into dst.The upper .unit = .L1, .L2, .S1, .S2 halfword of src1 is placed in the upper half-word of dst. The upperhalfword of src2 is placed in the lower halfword of dst. PACKH4 (.unit) src1, src2, Moves the high bytes of the two halfwords in dst src1 and src2, and packs theminto dst. The .unit = .L1 or .L2 bytes from src1 are packed into the most-significant bytes of dst,and the bytes from src2 are packed into the least-significant bytes of dst. PACKHL2 (.unit) src1, src2, Moves the upper halfword from src1 and the dst lower halfword from src2 andpacks them .unit = .L1, .L2, .S1, .S2 both into dst. The upper halfword of src1 is placed in the upper half-word of dst. The lower halfword of src2 is placed in the lower halfword of dst. PACKLH2 (.unit) src1, src2, Moves the lower halfword from src1, and the dst upper halfword from src2, andpacks them .unit = .L1, .L2, .S1, .S2 both into dst. The lower halfword of src1 is placed in the upperhalfword of dst. The upper halfword of src2 is placed in the lower halfword ofdst. PACKL4 (.unit) src1, src2, Moves the low bytes of the two halfwords in dst src1 and src2, and packs them intodst. The .unit = .L1 or .L2 bytes from src1 are packed into the most-significant bytes of dst, andthe bytes from src2 are packed into the least-significant bytes of dst. ROTL (.unit) src2, src1, dst Rotates the 32-bit value of src2 to the left, .unit = .M1 or .M2 and places the result in dst. Thenumber of bits to rotate is given in the 5 least-significant bits of src1. Bits 5through 31 of src1 are ignored and may be non-zero. SADD SADD (.unit) src1, src2, dst .unit = .L1, .L2, .S1, .S2 SADD2 SADDSU2 SADDUS2 SADDU4 SAT SET SHFL src1 is added to src2 and saturated, if an overflow occurs according to thefollowing rules:1)If the dst is an int and src1 + src2 > 231 -1, then the result is 231 -1. 2)If the dst is an int and src1 + src2 < -231 , then the result is -231 .3)If the dst is a long and src1 + src2 > 239-1 , then the result is 239 -1 4)If the dst is a long and src1 + src2 < -239 , then the result is -239.The result is placed in dst. If a saturate occurs, the SAT bit in the control statusregister (CSR) is set one cycle after dst is written. SADD2 (.unit) src1, src2, dst Performs 2s-complement addition between .unit = .S1 or .S2 signed, packed 16-bit quantitiesin src1 and src2. The results are placed in a signed, packed 16-bit format intodst. SADDSU2 (.unit) src2, src1, The SADDSU2 pseudo-operation performs dst 2s-complement addition betweenunsigned .unit = .S1 or .S2 and signed packed 16-bit quantities. The values in src1 are treatedas unsigned packed 16-bit quantities, and the values in src2 are treated assigned packed 16-bit quantities. The results are placed in an unsigned packed16-bit format into dst. The assembler uses the SADDUS2 (.unit) src1, src2, dstinstruction to perform this operation. SADDUS2 (.unit) src1, src2, Performs 2s-complement addition between dst unsigned, and signed, packed16-bit .unit = .S1 or .S2 quantities. The values in src1 are treated as unsigned, packed 16-bitquantities; and the values in src2 are treated as signed, packed 16-bit quanti-ties. The results are placed in an unsigned, packed 16-bit format into dst. SADDU4 (.unit) src1, src2, Performs 2s-complement addition between dst unsigned, packed 8-bit quantities.The values .unit = .S1 or .S2 in src1 and src2 are treated as unsigned, packed 8-bit quantitiesand the results are written into dst in an unsigned, packed 8-bit format. SAT (.unit) src2_h:src2_l, dst A 40-bit src2 value is converted to a 32-bit .unit = .L1 or .L2 value. If the value in src2 is greaterthan what can be represented in 32-bits, src2 is saturated. The result is placedin dst. If a saturate occurs, the SAT bit in the control status register (CSR) isset one cycle after dst is written. SET (.unit) src2, csta, cstb, For cstb > csta, the field in src2 as specified dst by csta to cstb is set to all 1s in dst. .unit = .S1 or .S2 SHFL (.unit) src2, dst Performs an interleave operation on the two .unit = .M1 or .M2 halfwords in src2. The bits in thelower halfword of src2 are placed in the even bit positions in dst, and the bitsin the upper halfword of src2 are placed in the odd bit positions in dst. SHL SHL (.unit) src2, src1, dst .unit = .S1 or .S2 SHLMB SHR SHR2 SHRMB SHRU SHRU2 SMPY SMPYH The src2 operand is shifted to the left by the src1 operand. The result is placedin dst. When a register is used, the six LSBs specify the shift amount and validvalues are 0-40. When an immediate is used, valid shift amounts are 0-31. SHLMB (.unit) src1, src2, dst Shifts the contents of src2 left by 1 byte, and .unit = .L1, .L2, .S1, .S2 then the most-significant byte ofsrc1 is merged into the least-significant byte position. The result is placed in dst. SHR (.unit) src2, src1, dst The src2 operand is shifted to the right by the .unit = .S1 or .S2 src1 operand. The sign-extendedresult is placed in dst. When a register is used, the six LSBs specify the shiftamount and valid values are 0-40. When an immediate value is used, validshift amounts are 0-31 SHR2 (.unit) src2, src1, dst Performs an arithmetic shift right on signed, .unit = .S1 or .S2 packed 16-bit quantities. Thevalues in src2 are treated as signed, packed 16-bit quantities. The lower 5 bitsof src1 are treated as the shift amount. The results are placed in a signed,packed 16-bit format into dst. SHRMB (.unit) src1, src2, Shifts the contents of src2 right by 1 byte, and dst then the least-significant byteof src1 is .unit = .L1, .L2, .S1, .S2 merged into the most-significant byte position. The result is placedin dst. SHRU (.unit) src2, src1, dst The src2 operand is shifted to the right by the .unit = .S1 or .S2 src1 operand. Thezero-extended result is placed in dst. When a register is used, the six LSBsspecify the shift amount and valid values are 0-40. When an immediate valuis used, valid shift amounts are 0-31 SHRU2 (.unit) src2, src1, dst Performs an arithmetic shift right on .unit = .S1 or .S2 unsigned, packed 16-bit quantities. Thevalues in src2 are treated as unsigned, packed 16-bit quantities. The lower5 bits of src1 are treated as the shift amount. The results are placed in anunsigned, packed 16-bit format into dst. SMPY (.unit) src1, src2, dst The least significant 16 bits of src1 operand is .unit = .M1 or .M2 multiplied by the least significant16 bits of the src2 operand. The result is left shifted by 1 and placed in dst. Ifthe left-shifted result is 80000000h, then the result is saturated to7FFFFFFFh. If a saturate occurs, the SAT bit in CSR is set one cycle after dstis written. The source operands are signed by default. SMPYH (.unit) src1, src2, dst The most significant 16 bits of src1 operand .unit = .M1 or .M2 is multiplied by the most significant 16 bits of the src2 operand. The result is left shifted by 1 and placed in dst. If the left-shifted result is 80000000h, then the result is saturated to 7FFFFFFFh. If a saturation occurs, the SAT bit in CSR is set one cycle after dst is written. The source operands are signed by default. SMPYHL SMPYHL (.unit) src1, src2, dst .unit = .M1 or .M2 SMPYLH SMPYLH (.unit) src1, src2, dst .unit = .M1 or .M2 SMPY2 SMPY2 (.unit) src1, src2, dst_o:dst_e .unit = .M1 or .M2 SPACK2 SPACK2 (.unit) src1, src2, dst .unit = .S1 or .S2 SPACKU4 SPACKU4 (.unit) src1, src2, dst .unit = .S1 or .S2 SSHL (.unit) src2, src1, dst .unit = .S1 or .S2 SSHL SSHVL SSHVR SSHVL (.unit) src2, src1, dst .unit = .M1 or .M2 SSHVR (.unit) src2, src1, dst .unit = .M1 or .M2 The most significant 16 bits of the src1 operand is multiplied by the least signifi-cant bits of the src2 operand. The result is left shifted by 1 and placed in dst.If the left-shifted result is 80000000h, then the result is saturated to 7FFFFFFFh. If a saturation occurs, the SAT bit in CSR is set one cycle afterdst is written. The least significant 16 bits of the src1 operand is multiplied by the most sigificant 16 bits of the src2 operand. The result is left shifted by 1 and placed in dst. If the left-shifted result is 80000000h, then the result is saturated to 7FFFFFFFh. If a saturation occurs, the SAT bit in CSR is set one cycle after dst is written. Performs two 16-bit by 16-bit multiplies between two pairs of signed, packed16-bit values, with an additional left-shift and saturate. The values in src1 andsrc2 are treated as signed, packed 16-bit quantities. The two 32-bit results arewritten into a 64-bit register pair. Takes two signed 32-bit quantities in src1 and src2 and saturates them to signed 16-bit quantities. The signed 16-bit results are then packed into a signed, packed 16-bit format and written to dst. Specifically, the saturated 16-bit signed value of src1 is written to the upper halfword of dst, and the saturated 16-bit signed value of src2 is written to the lower halfword of dst. Takes four signed 16-bit values and saturates them to unsigned 8-bitquantities. The values in src1 and src2 are treated as signed, packed 16-bitquantities. The results are written into dst in an unsigned, packed 8-bit format. The src2 operand is shifted to the left by the src1 operand. The result is placedin dst. When a register is used to specify the shift, the five least significant bitsspecify the shift amount. Valid values are 0 through 31, and the result of theshift is invalid if the shift amount is greater than 31. The result of the shift issaturated to 32 bits. If a saturate occurs, the SAT bit in CSR is set one cycleafter dst is written. Shifts the signed 32-bit value in src2 to the left or right by the number of bitsspecified by src1, and places the result in dst. Shifts the signed 32-bit value in src2 to the left or right by the number of bitsspecified by src1, and places the result in dst. SSUB SSUB (.unit) src1, src2, dst .unit = .L1 or .L2 STB memory STB memory (15-bit offset) STB(.unit) src, *+baseR[ucst5] .unit = .D1 or .D2 STB(.unit)src,*+ B14/B15[ucst15] .unit = .D2 src2 is subtracted from src1 and is saturated to the result size according to thefollowing rules:1)If the dst is an int and src1 - src2 > 231 -1, then the result is 231 -1. 2)If the dst is an int and src1 - src2 < -231 , then the result is -231 .3)If the dst is a long and src1 - src2 > 239-1 , then the result is 239 -1 4)If the dst is a long and src1 - src2 < -239 , then the result is -239.The result is placed in dst. If a saturate occurs, the SAT bit in CSR is setone cycle after dst is written. Stores a byte to memory from a general-purpose register (src). Stores a byte to memory from a general-purpose register (src). The memoryaddress is formed from a base address register B14 (y = 0) or B15 (y = 1) andan offset, which is a 15-bit unsigned constant (ucst15). The assembler selectsthis format only when the constant is larger than five bits in magnitude. Thisinstruction executes only on the .D2 unit. Stores a 64-bit quantity to memory from a 64-bit register, src STDW STH memory STH memory (15-bit offset) Register Offset STDW(.unit)src,*+ baseR[offsetR] Unsigned Constant Offset STDW(.unit)src,*+baseR[ucst5] .unit = .D1 or .D2 Register Offset STH(.unit)src,*+ baseR[offsetR] Unsigned Constant Offset STH(.unit) src, *+baseR[ucst5] .unit = .D1 or .D2 STH(.unit)src,*+ B14/B15[ucst15] .unit = .D2 Stores a halfword to memory from a general-purpose register (src). STNDW Register Offset STNDW(.unit)src,*+ baseR[offsetR] Unsigned Constant Offset STNDW(.unit)src,*+ baseR[ucst5] .unit = .D1 or .D2 Stores a halfword to memory from a general-purpose register (src). Thememory address is formed from a base address register B14 (y = 0) orB15 (y = 1) and an offset, which is a 15-bit unsigned constant (ucst15). Theassembler selects this format only when the constant is larger than five bits inmagnitude. This instruction executes only on the .D2 unit. Stores a 64-bit quantity to memory from a 64-bit register pair, src STNW STW memory STW memory (15-bit offset) Register Offset STNW(.unit)src,*+ baseR[offsetR] Unsigned Constant Offset STNW(.unit)src,*+ baseR[ucst5] .unit = .D1 or .D2 Register Offset STW(.unit)src,*+ baseR[offsetR] Unsigned Constant Offset STW(.unit)src, *+baseR[ucst5] .unit = .D1 or .D2 STW(.unit)src,*+B14/B15[ucst15] .unit = .D2 Stores a 32-bit quantity to memory from a 32-bit register, src. Stores a word to memory from a general-purpose register (src). SUB SUBAB SUBABS4 SUBAH SUBAW SUB (.unit) src1, src2, dst .unit= .D1, .D2, .L1, .L2, .S1, .S2 SUBAB (.unit) src2, src1, dst src1 is subtracted from src2 using the byte .unit = .D1 or .D2 addressing mode specified for src2.The subtraction defaults to linear mode. However, if src2 is one of A4-A7 orB4-B7, the mode can be changed to circular mode by writing the appropriatevalue to the AMR (see section 2.7.3, page 2-12). The result is placed in dst. SUBABS4(.unit) src1, src2, Calculates the absolute value of the dst differences between the packed 8-bit .unit = .L1 or .L2 datacontained in the source registers. The values in src1 and src2 are treated asunsigned, packed 8-bit quantities. The result is written into dst in an unsigned,packed 8-bit format. SUBAH (.unit) src2, src1, dst src1 is subtracted from src2 using the .unit = .D1 or .D2 halfword addressing mode specified forsrc2. The subtraction defaults to linear mode. However, if src2 is one of A4-A7or B4?B7, the mode can be changed to circular mode by writing the appropriate value to the AMR. src1 is left shifted by 1.The result is placed in dst. SUBAW (.unit) src2, src1, src1 is subtracted from src2 using the word dst addressing mode specified forsrc2. The .unit = .D1 or .D2 subtraction defaults to linear mode. However, if src2 is one of A4-A7or B4-B7, the mode can be changed to circular mode by writing the appropri-ate value to the AMR . src1 is left shifted by 2.The result is placed in dst. Stores a word to memory from a general-purpose register (src). The memoryaddress is formed from a base address register B14 (y = 0) or B15 (y = 1) andan offset, which is a 15-bit unsigned constant (ucst15). The assembler selectsthis format only when the constant is larger than five bits in magnitude. Thisinstruction executes only on the .D2 unit. src2 is subtracted from src1. The result is placed in dst. SUBC SUBC (.unit) src1, src2, dst .unit = .L1 or .L2 SUBU SUB2 SUBU (.unit) src1, src2, dst .unit = .L1 or .L2 SUB2 (.unit) src1, src2, dst .unit = .L1, .L2, .S1, .S2, .D1, .D2 SUB4 SUB4 (.unit) src1, src2, dst .unit = .L1 or .L2 SWAP2 SWAP2 (.unit) src2, dst .unit = .L1, .L2, .S1, .S2 SWAP4 SWAP4 (.unit) src2, dst .unit = .L1 or .L2 UNPKHU4 (.unit) src2, dst .unit = .L1, .L2, .S1, .S2 UNPKLU4 (.unit) src2, dst.unit = .L1, .L2, .S1, .S2 XOR (.unit) src1, src2, dst .unit= .L1,.L2,.S1,.S2,.D1,.D2 XPND2 (.unit) src2, dst .unit = .M1 or .M2 UNPKHU4 UNPKLU4 XOR XPND2 Subtract src2 from src1. If result is greater than or equal to 0, left shift resultby 1, add 1 to it, and place it in dst. If result is less than 0, left shift src1 by 1,and place it in dst. This step is commonly used in division. src2 is subtracted from src1. The result is placed in dst. The upper and lower halves of src2 are subtracted from the upper and lowerhalves of src1 and the result is placed in dst. Any borrow from the lower-halfsubtraction does not affect the upper-half subtraction. Specifically, theupper-half of src2 is subtracted from the upper-half of src1 and placed in theupper-half of dst. The lower-half of src2 is subtracted from the lower-half ofsrc1 and placed in the lower-half of dst. Performs 2s-complement subtraction between packed 8-bit quantities. Thevalues in src1 and src2 are treated as packed 8-bit data and the results arewritten into dst in a packed 8-bit format. The SWAP2 pseudo-operation takes the lower halfword from src2 and placesit in the upper halfword of dst, while the upper halfword from src2 is placed inthe lower halfword of dst. Exchanges pairs of bytes within each halfword of src2, placing the result in dst.The values in src2 are treated as unsigned, packed 8-bit values. Moves the two most-significant bytes of src2 into the two low bytes of the twohalfwords of dst. Moves the two least-significant bytes of src2 into the two low bytes of the twohalfwords of dst. Performs a bitwise exclusive-OR (XOR) operation between src1 and src2.The result is placed in dst. The scst5 operands are sign extended to 32 bits. Reads the two least-significant bits of src2 and expands them into two halfwordmasks written to dst. Bit 1 of src2 is replicated and placed in the upper halfwordof dst. Bit 0 of src2 is replicated and placed in the lower halfword of dst. Bits 2through 31 of src2 are ignored. XPND4 XPND4 (.unit) src2, dst .unit = .M1 or .M2 ZERO ZERO (.unit) dst .unit = .L1, .L2, .D1, .D2, .S1, .S2 Reads the four least-significant bits of src2 and expands them into four-bytemasks written to dst. Bit 0 of src2 is replicated and placed in theleast-significant byte of dst. Bit 1 of src2 is replicated and placed in secondleast-significant byte of dst. Bit 2 of src2 is replicated and placed in secondmost-significant byte of dst. Bit 3 of src2 is replicated and placed inmost-significant byte of dst. Bits 4 through 31 of src2 are ignored. This is a pseudo-operation used to fill the destination register or register pairwith 0s.