SPR4096A数据手册V1.2

来源：二三娱乐

SPR4096ASP 512K x8BitsBusFlash OCT. 01, 2003 Version 1.2 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.

SPR4096A

Table of Contents

PAGE

1. GENERAL DESCRIPTION..........................................................................................................................................................................3 2. FEATURES..................................................................................................................................................................................................3 3. BLOCK DIAGRAM......................................................................................................................................................................................3 4. SIGNAL DESCRIPTIONS...........................................................................................................................................................................5 4.1. ORDERING INFORMATION.......................................................................................................................................................................5 5. FUNCTIONAL DESCRIPTIONS..................................................................................................................................................................6 5.1. BUS MEMORY INTERFACE (BMI)............................................................................................................................................................6 5.1.1. BMI description.........................................................................................................................................................................6 5.1.2. BMI AC characteristics..............................................................................................................................................................7 5.1.3. BMI configuration setting..........................................................................................................................................................8 5.1.4. BMI register description............................................................................................................................................................9 5.1.5. BMI memory mapping...............................................................................................................................................................9 5.1.6. BMI command sequence........................................................................................................................................................10 5.2. SERIAL INTERFACE (SIF)......................................................................................................................................................................16 5.2.1. BIT transfer.............................................................................................................................................................................16 5.2.2. Instruction set..........................................................................................................................................................................17 5.2.3. SIF AC characteristics.............................................................................................................................................................18 6. ELECTRICAL SPECIFICATIONS.............................................................................................................................................................20 6.1. ABSOLUTE MAXIMUM RATINGS.............................................................................................................................................................20 6.2. RECOMMENDED DC OPERATING CONDITIONS (VDDQ = 2.25V - 3.6V, VDDI = 2.25V - 2.75V, TA = 0 - 70℃)............................................20 6.3. DC ELECTRICAL CHARACTERISTICS (VDDQ = 2.25V - 3.6V, VDDI = 2.25V - 2.75V, TA = 0 - 70℃)...........................................................20 7. APPLICATION CIRCUITS.........................................................................................................................................................................21 7.1. POWER SUPPLY VOLTAGE....................................................................................................................................................................21 7.2. BUS INTERFACE...................................................................................................................................................................................22 7.2.1. Cascade access mode (type A, C, G).....................................................................................................................................22 7.2.2. Bus Interface...........................................................................................................................................................................23 7.3. SERIAL INTERFACE...............................................................................................................................................................................24 8. PACKAGE / PAD LOCATIONS.................................................................................................................................................................25 9. DISCLAIMER.............................................................................................................................................................................................26 10. REVISION HISTORY.................................................................................................................................................................................28

2 OCT. 01, 2003Version: 1.2

SPR4096A

512K X 8 BITS BUS FLASH

1. GENERAL DESCRIPTION

SPR4096A embeds 512K x 8-bit high performance bus flash memory and 4K x 8-bit SRAM. In the embedded Bus Memory Interface (BMI) and a Serial Interface, SPR4096A allows SPL13X & SPLB3X MCU to access FLASH/SRAM memory via BMI or 1-bit serial mode. In SPR4096A, two power types are offered - VDDI and VDDQ. The VDDI, ranged between 2.25V to 2.75V, is the power supply for internal FLASH memory and logical control components. The VDDQ, ranged from 2.25V to 3.6V, is the power supply to I/O only. SPR4096A is able to operate up to 5.0MHz. Its maximum read current is 2mA and maximum program/erase current is 6.0mA.

3. BLOCK DIAGRAM

The SPR4096A contains six components: Bus Memory Interface (BMI), Serial Interface (SIF), timer, 32K-bit SRAM, program & erase controller (PECON), and a 4M-bit FLASH memory. The CF0 - CF7 define the memory configuration. When BMI is selected, MC0 and MC1 act as write/read control signal, and AD[7:0] is bi-direction address/data bus. BMI processes these signals and generates control signals and address/data for FLASH or SRAM write/read. If BMI receives PROGRAM, ERASE or MASS ERASE command for FLASH, it forwards these commands to PECON for command execution. When SIF is selected, SCK behaves as serial clock and SDA as 1-bit serial I/O. If FLASH read or SRAM write/read command is received, SIF is capable of writing to/reading from the embedded memory directly. However, if PROGRAM, ERASE or MASS ERASE for FLASH is received, SIF also forwards these commands to PECON. When EPCON is active, it needs a 200KHz clock (provided by the CLK block shown in block diagram).

2. FEATURES

󰂄 512K x 8 bits FLASH, 256 sectors and 2K bytes per sector. 󰂄 Endurance: 20,000 Cycles (min)

󰂄 Data Retention: 10 years under Room Temperature 󰂄 4K x 8 bits SRAM.

󰂄 Supply voltage: VDDQ: 2.25V ~ 3.6V, VDDI: 2.25V ~ 2.75V. 󰂄 Maximum operating frequency: Bus Interface and serial interface at 5.0MHz.

󰂄 Operating current: 6.0mA (max). 󰂄 Standby current: 4.0µA (max).

󰂄 Concurrent SRAM write/read while erasing/programming FLASH.

󰂄 Fast page programming mode (16 bytes).

󰂄 Cascade application is available for both Bus and Serial Interface.

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SPR4096A

sce,soe,sweCF[7:0]MC0MC1FLASH DoutAD[7:0]512K x 8FLASHSRAM Doutbus memoryinterface4K x 8 SRAMRSTBSCKSDADinserialinterfaceaddressce,oe,weprogram &erasecontrollerDinAddrCntlCLK ,T=5us © Sunplus Technology Co., Ltd. Proprietary & Confidential 4 OCT. 01, 2003Version: 1.2

SPR4096A

4. SIGNAL DESCRIPTIONS

Mnemonic PIN No. CF0 - CF7 AD0 - AD7 MC0 - MC1 30 - 23 12 - 19 7 - 8 Configuration bonding option. Bus Interface address/data I/O. Bus Interface write/read control signal. Description RESET SCK SDA VDDQ VDDI VSS VSSQ

3 4 10 20 9 1, 6 11 Reset (low active). Serial Interface clock. Serial Interface data I/O. Power supply for 3.3V device. Power supply for 2.5V device. Ground 4.1. Ordering Information

Product Number

Package Type

SPR4096A-NnnV-C Chip form Note1: Code number is assigned for customer.

Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).

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5. FUNCTIONAL DESCRIPTIONS

5.1. BUS Memory Interface (BMI) 5.1.1. BMI description

When Bus Memory Interface is used, the pins should be connected as follows: Name Description

MC1 MC0 AD BUS L L

L H

Data for Write Data for Read

AL CF0 - CF7 AD0 - AD7 MC0 - MC1 RESET Configuration bonding option Bus Interface address/data I/O Bus Interface write/read control signal Reset (low active) H L AH: high byte address AL: low byte address.

H H AH SCK Not connected SDA Not connected VDDQ VDDI VSS, VSSQ

Power supply for 3.3V device. Power supply for 2.5V device. Ground

The timing waveform is as follows: Read Cycle:MC0MC1ADAHALDATA for readMC0Bus FlashSPR512SPR1024SPR4096MC1AD0-AD7ControllerSPL13xSPLB3xWrite Cycle:MC0MC1Bus Interface Block diagram of bus flash and BMI controller

ADAHALDATA for write

BMI is an interface between SPR4096A and SPL13X or SPLB3X MCU. It provides flexible and efficient memory management. BMI contains an 8-bit bi-directional Address/Data bus, ADbus, which is multiplexed by two control signals - MC0 and MC1. The relationship of Bus flash and BMI controller is shown above. MC0 configures the operation mode (Read or Write), and MC1 determines whether the ADbus is an address or a data bus. The MC0 and MC1 decoded table is depicted as follows:

MC0 falling edge => latch AH. MC1 falling edge => (1) latch AL.

(2) if MC0 = 1 then READ, if MC0 = 0 then WRITE. DATA for WRITE.

MC1 rising edge => if READ then set ADbus to HiZ. if WRITE then latch

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5.1.2. BMI AC characteristics

Read CycleCPU_CKtMC0HT/4MC0tM1M0tPM1MC1T/2tM0AStM0AHtM1ALtRHZADAHALDATA for READWrite CycletMC0HMC0tMCWT/2tM0AStMCAHtWHZMC1tMCALADAHALDATA for Write 5.1.2.1. AC characteristics (VDD = 2.85V - 3.15V , TA = 0 - 70℃) Characteristics Symbol Min. Typ. Max. Unit MC1 period High period of MC0 AH setup time MC0 falling to AH end MC1 rising to MC0 falling MC1 falling to AL end MC1 rising to AD Hi-Z (W) MC1 rising to AD Hi-Z (R) Data latch to MC1 rising MC0 rising to MC1 rising T 200 - - - - - - ns ns ns ns TMC0H 20 TM0AS 10 - TM0AH 10 TM1M0 - - - 15 ns TM1AL 10 - 35 ns TWHZ 10 - - ns TRHZ - - 5.0 ns TPM1 - 25 - ns TMCW - 15 - ns © Sunplus Technology Co., Ltd. Proprietary & Confidential 7 OCT. 01, 2003Version: 1.2

SPR4096A

CF[7:3] determines the bank control register ($00) configuration and SRAM allocation area, see the Table 2 for detailed setups. Note that the change of bank is accomplished by given the corresponding value to the $00. For example, to access the Bank0, a value of “00h” must be given to $00 in addition to a logic value of “10000” should be given to the external pins, CF[7:3].

5.1.3. BMI configuration setting

The Bus Memory Interface (BMI) has four modes, A, C, E, and G in which volume IDs are “00”, “01”, “xx”, and “01” respectively, where “xx” represents “don’t care”. The configuration settings are illustrated in the CF[2:0], where CF indicates the physical pins, see Table 1. For the physical pins, simply apply logic high (1) or low (0) to the pins to participate the settings. Moreover, the

Table 1: CF[2:0], configuration of BMI mode.

BMI Type

CF2

CF1

CF0

Volume ID $0D[1:0]

A 0 0 0 00 C 0 1 0 01 E 1 0 0 xx G 1 1 0 01

Table 2: CF[7:3], configuration of bank setting and SRAM allocation. “b” is for extender memory bank select.

BMI Type

CF7

CF6

CF5

CF4

CF3

Flash Bank Switch

SRAM allocation

1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 A, C, E

1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 X X 0 0 0 X X 0 0 1 X X 0 1 0 G

X X 0 1 1 X X 1 0 0 X X 1 0 1 X X 1 1 0 X X 1 1 1

0000bbbb 0001bbbb 0010bbbb 0011bbbb 0100bbbb 0101bbbb 0110bbbb 0111bbbb 1000bbbb 1001bbbb 1010bbbb 1011bbbb 1100bbbb 1101bbbb 1110bbbb 1111bbbb 1000bbbb 1001bbbb 1010bbbb 1011bbbb 1100bbbb 1101bbbb 1110bbbb 1111bbbb

$2000~2FFF $3000~3FFF $2000~2FFF $3000~3FFF $2000~2FFF $3000~3FFF $2000~2FFF $3000~3FFF $2000~2FFF $3000~3FFF $2000~2FFF $3000~3FFF $2000~2FFF $3000~3FFF $2000~2FFF $3000~3FFF N/A N/A N/A N/A N/A N/A N/A N/A

Proprietary & Confidential

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SPR4096A

5.1.4.3. External memory mapping ($0B.1 , EXC)

b7 b6 b5 b4 b3 b2 b1 b0

5.1.4. BMI register description

The BMI uses MCU address from 4000h to FFFFh and duplicates some registers of SPL13X and SPLB3X into SPR4096A as bank switch. The register usage and mapping table is as below.

- - - - - - EXC

CPU address mapping of $C000 - $FFFF. b1 : EXC = 0: Map to internal ROM

= 1: Map to external Bus Flash

- 5.1.4.1. Memory bank switch ($00, BSW)

b7 b6 b5 b4 b3 b2 b1 b0 Note: SUNPLUS recommend “always” keep this bit to “0” when bus flash is

applied.

* * * * BSW3 BSW2 BSW1BSW0

* $00[7:4] must be set the same value as the physical logic setting of CF[6:3]

5.1.4.4. Flash writing protection ($18.2 , PT)

b7 b6 b5 b4 b3 b2 b1 b0

5.1.4.2. Volume ID ($0D , VOL)

b7 b6 b5 b4 b3 b2 b1 b0 - - - - - PT - - Write-protect for the beginning 1M bit Flash when using Bus Interface. (Serial Interface don’t support write protect function) b1: PT = 0: enabled (default) 1: disabled

- - - - - 1 VOL1

VOL0

=[AH,AL]$2000 - $2FFFMCU ViewSRAM ViewRAM0CF3RAM$3000 - $3FFFFLASH View0 H0$4000 - $7FFFROM(Bank)L11 L162$8000 - $BFFFROM(Bank)H. . .2 L2 H0 L1 H$00000 - $03FFF$04000 - $07FFF$08000 - $0BFFF$0C000 - $0FFFF$10000 - $13FFF$14000 - $17FFF14KB$000 - $FFF5.1.5. BMI memory mapping

15 H1515 L$18000 - $1BFFF$1C000 - $1FFFF © Sunplus Technology Co., Ltd. Proprietary & Confidential

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SPR4096A

5.1.6. BMI command sequence

5.1.6.1. Bus memory interface command sequence

Command sequence

Bus cycle

5 th

6 addr Datath

Addr Data addr Data addr Data addr Data Read device ID 5555h AAh AAAAh 55h 5555h90h

8000h/8001hAny addr.

ID (read)Status

(1)

Read status Return to normal mode (RESET)

5555h AAh AAAAh 55h 5555h70h

XXXX F0h RD

Read RA (read)Byte program

5555h

AAh

55h

5555h

A0h

(2)

(3)

(4)

AAAAh PA PD

Page program 5555h AAh AAAAh 55h 5555hSector Erase 5555h AAh AAAAh 55h 5555hMass erase

5555h AAh AAAAh 55h 5555h

Note1: Status: b7 for 0/1: busy/ready, b0 for 0/1: write enable/write protect. Note2: PA: program byte address Note3: PD: program data Note4: EA: sector erase address

B0h PA0 PD0 --- --- PAn PDn 80h 5555h88h 5555h

AAh AAAAh 55h EA 30h AAh AAAAh 55h 5555h

10h

5.1.6.2. Read device ID command output

Manufacture’s code Device code

Address Data 00000h 00001h

C7h D7h

5.1.6.3. BMI read command sequence StartFLASH is already at normal operationWrite VOL(000D[2:0])Write BSWRead data fromaddressRead completed

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5.1.6.4. BMI byte program command sequence StartFLASH is already at normal operationWrite VOLWrite BSWWrite data AAh to address 5555hWrite data 55h to address AAAAhEnter program modeWrite data A0h to address 5555hProgram data to addressEnter status-polling mode FLASH accept no command (includingRESET command) when it's busy.Read any byteNoBit7=1?YesReady status: accept RESET command onlyProgram completedProgram time: 45us ~ 60usWrite F0h to any addressExit from status-pollingDetect end of programmingReturn to normal mode

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SPR4096A

5.1.6.5. BMI page (16 bytes) program command sequence StartFLASH is already at normal operationWrite VOLWrite BSWWrite data AAh to address 5555hWrite data 55h to address AAAAhEnter page program modeWrite data B0h to address 5555hWrite DATA0 to ADDR0ADDR0=XXXX0h?YesNo ( write protect )Bit0=0?YesNoNoAbort, return to normalmodefirst 1M?Write DATAn to ADDRnYesNon=Fh?YesRead any byteNoWrite data F0h to any NOT relativeADDRAbort, returnto normalmodeNoBit7=1?YesReady status: accept reset onlyDetect end of programmingProgram completedProgram time: 345us ~ 460usWrite F0h to any addressExit from status-pollingReturn to normal mode © Sunplus Technology Co., Ltd. Proprietary & Confidential 12 OCT. 01, 2003Version: 1.2

SPR4096A

5.1.6.6. BMI sector (2K bytes) erase command sequence StartFLASH is already at normal operationWrite volume IDWrite bank 00Write data AAh to address 5555hEnter sector erase modeWrite data 55h to address AAAAhWrite data 80h to address 5555hWrite data AAh to address 5555hWrite data 55h to address AAAAhWrite data 30h to sector address (EA) which is going to beerasedRead any byteEnter status-polling mode FLASH, no command accepted (includingRESET command) when it's busy.NoBit7=1?YesReady status: accept reset onlyErase completedErase time: 27msWrite F0h to any addressExit from status-pollingDetect end of eraseReturn to normal mode

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5.1.6.7. BMI mass erase command sequence StartFLASH is already at normal operationWrite VOLWrite BSWWrite data AAh to address 5555hEnter mass-erase modeWrite data 55h to address AAAAhWrite data 88h to address 5555hWrite data AAh to address 5555hWrite data 55h to address AAAAhWrite data 10h to address 5555hRead any byteEnter status-polling mode FLASH no command accepted (includingRESET command) when it's busy.NoBit7=1?YesReady status: accept reset onlyErase completedErase time: 70msWrite F0h to any addressExit from status-pollingDetect end of eraseReturn to normal mode

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5.1.6.8. Enter status-polling mode from normal mode StartFLASH is already at normal operationERASE procedure (sector erase, masserase or information block erase)Sector erase time = 27msMass erase time = 70msNoVerify the entire memory arrayto be FFh or notYesERASE procedureAdd 1 phase after verify erase OKErase completed 5.1.6.9. Erase algorithm for improving endurance performance StartFLASH is already at normal operationERASE procedure (sector erase, masserase or information block erase)Sector erase time = 27msMass erase time = 70msNoVerify the entire memory arrayto be FFh or notYesERASE procedureAdd 1 phase after verify erase OKErase completed © Sunplus Technology Co., Ltd. Proprietary & Confidential 15 OCT. 01, 2003Version: 1.2

SPR4096A

5.2. Serial Interface (SIF)

Using serial interface, PINs should be configured as follows: Name Description CF0 - CF2 CF3 - CF4 CF7 AD0 - AD7 MC0 - MC1 RESET Set CF[2:0] = 111 to select SIF Cascade SIF configuration FLASH/SRAM selector (0:FLASH, 1:SRAM) Not connected Not connected Reset (low active) SCK Serial clock SDA VDDQ VDDI VSS, VSSQ Note: PIN CF3 and CF4 are internal pull-low.

Serial data I/O Power supply for 3.3V device. Power supply for 2.5V device. Ground

5.2.1. BIT transfer

One clock pulse is generated for each data bit transferring. The data on SDA line must be stabilized during the clock HIGH period. The HIGH or LOW state of the data line can only be changed when the clock signal on the SCK line is LOW.

SCKSDAdata line stable;data valid Within the procedure of the SUNPLUS Serial Interface, unique conditions (defined as START (S) and STOP (P)) arise. A HIGH to LOW transition on SDA line while SCK is HIGH indicates a START condition. A LOW to HIGH transition on SDA line while SCK is HIGH defines a STOP condition. change of dataallowedSCKSDASTART condition (S) STOP condition (P)© Sunplus Technology Co., Ltd. Proprietary & Confidential 16 OCT. 01, 2003Version: 1.2

SPR4096A

5.2.2. Instruction set

5.2.2.1. READ with random address access (CF7 = 0: FLASH, CF7 = 1: SRAM)

FLASH READ command composes of a start bit followed by: a 4-bit opcode (A[24:21] = 1000), a 2-bit memory selection, and a 19-bit address (A[18:0]) location. After receiving FLASH READ command, the SDA line should be set to high-impedance. SPR4096A will begin shifting out the data addressed (MSB first)

STARTS1000CF4CF3A18 ~ A0D7 ~ D0on the falling edge of the SCK clock and the output data bit will be stable after the specified time delay (tACC). After 8 data bits are shifted out, a stop bit is required to terminate the command. SRAM READ command is the same as FLASH READ except CF7 = 1.

STOPP 5.2.2.2. READ with auto-address-count (CF7 = 0: FLASH, CF7 = 1: SRAM) FLASH READ with auto-address-count command is the same as FLASH READ except no stop bit is inserted before the next SCK falling edge, after the first 8 data bits are shifted out. SPR4096A will automatically increment the address by 1 and its data content will be shifted out proceeded by the clock cycle. The procedure continues until a stop bit is received. SRAM READ with auto-address-count command is the same as FLASH READ with auto-address-count except CF7 = 1. addrS1000CF4CF3A18 ~ A0D7 ~ D0addr+nD7 ~ D0P 5.2.2.3. BYTE program (CF7 = 0: FLASH, CF7 = 1: SRAM) FLASH BYTE PROGRAM command is a start bit followed by: a 4-bit opcode (A[24:21] = 0000), a 2-bit memory selection, a 19-bit address location (A[18:0]), and an 8-bit data (D[7:0]). After receiving FLASH BYTE PROGRAM command, a specified interval S0000CF4CF3A18 ~ A0D7 ~ D0P+ wait 60us(tPGM) is necessary to program data into FLASH. After all, a stop bit terminates the command. SRAM WRITE command is the same as FLASH BYTE PROGRAM except CF7 = 1 and no wait time is necessary. 5.2.2.4. Flash sector erase FLASH SECTOR ERASE command is a start bit followed by: a 4-bit opcode (A[24:21] = 0100), a 2-bit memory selection, and a 19-bit address location (A[18:0]). The A18 to A11 determines which sector to be erased. The A10 to A0 are “DON’T CARE”. After receiving FLASH SECTOR ERASE command, a specified interval (tERASE) is needed to erase the selected sector of the FLASH. After that, a stop bit terminates the command. S 0100CF4CF3A18 ~ A0P+ wait 24ms© Sunplus Technology Co., Ltd. Proprietary & Confidential 17 OCT. 01, 2003Version: 1.2

SPR4096A

interval (tMASS) is needed to erase the information block and/or main block of the FLASH. Finally, a stop bit terminates the command.

5.2.2.5. Flash mass erase

FLASH MASS ERASE command is a start bit followed by: a 4-bit opcode (A[24:21] = 0110), a 2-bit memory selection and a 19-bit address location (A[18:0]). The A18 to A0 are “DON’T CARE”. After receiving main block MASS ERASE command, a specified S0110CF4CF3A18 ~ A0P+ wait 70ms 5.2.3. SIF AC characteristics 5.2.3.1. AC characteristics (VDD = 2.85V - 3.15V, TA = 0 - 70℃) Characteristic Symbol Max. Min. Unit Period of SCK Low period of SCK clock High period of SCK clock Address setup time Address hold time READ access time READ data hold time PROGRAM data setup time PROGRAM data hold time PROGRAM time ERASE time MASS ERASE time Rise time of SCK Fall time of SCK Rise time of SDA Fall time of SDA tC - 200 ns tLOW - 85 ns tHIGH - 85 ns tAS - 15 ns tAH - 15 ns tACC 35 15 ns tDH - 15 ns tPDS - 15 ns tPDH - 15 ns tPGM - 60 µs tERASE - 24 ms tMASS - 70 ms tRCK 15 - ns tFCK 15 - ns tRDA 15 - ns tFDA 15 - ns tFCKtRCKSCKtFDAtRDASDAstartstop© Sunplus Technology Co., Ltd. Proprietary & Confidential 18 OCT. 01, 2003Version: 1.2

SPR4096A

1). Read Command SCKtACCSDAA24A23A0D7D6D5D4D3D2D1D0tDHstartstop

2). Read Command with Auto-Address-Count tCSCKtASSDAA24A23tHIGHtLOWtAHA0D7D6D0D7D0D7D0D7D0addrstartaddr+1addr+nstop

3). Program Command SCKtPDSSDAA24A23A0D7D6D0+ wait time = tPGMtPDHstart 4). Sector Erase and Mass Erase Command stopSCK+ wait time = tERASE or tMASSSDAA24A23A2A1A0start stop© Sunplus Technology Co., Ltd. Proprietary & Confidential 19 OCT. 01, 2003Version: 1.2

SPR4096A

6. ELECTRICAL SPECIFICATIONS

6.1. Absolute Maximum Ratings

Characteristics Symbol Ratings Ambient Operating Temperature Storage Temperature

Supply Voltage to Ground Potential Output Voltage Input Voltage

conditions see AC/DC Electrical Characteristics.

TA TSTG VDD VOUT VIN

-10℃ ~ 80℃ -65℃ ~ 150℃ -0.4V ~ 4.0V -0.4V ~ VDD + 0.4V -0.4V ~ VDD + 0.4V

Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational

6.2. Recommended DC Operating Conditions (VDDQ = 2.25V - 3.6V, VDDI = 2.25V - 2.75V, TA = 0 - 70℃)

Limit

Characteristics Symbol Min. Typ. Max. Unit

External Supply Voltage Internal Supply Voltage Supply Voltage Input High Voltage Input Low Voltage

VDDQ 2.25 3.0 3.6 V VDDI 2.25 2.5 2.75 V VSS

0.0

V V

VIH 2.2 - VDD + 0.3

VIL -0.3 - 0.4 V 6.3. DC Electrical Characteristics (VDDQ = 2.25V - 3.6V, VDDI = 2.25V - 2.75V, TA = 0 - 70℃)

Limit

Characteristic Symbol Unit Test Condition Min. Typ. Max. Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Operating Supply Current (f = 5.0MHz), CL = 80pF Standby Current (CMOS)

VOH 2.3 - - V IOH = -1.0mA VOL - - 0.3 V IOL = 1.0mA II(L) - - 1.0 µA IO(L) - - 1.0 µA ICC - - 6.0 mA ISB - - 4.0 µA

MC0 = MC1 = VDDQ, AD[0:7] = VSS

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7. APPLICATION CIRCUITS

7.1. Power Supply Voltage

VSUPPLY (working voltage) > 2.75V

VDDQ = VSUPPLY, VDDI = Voltage dropped by diode VPP = NC, VSS = VSSQ = GND VSUPPLY(3.0V)VDDQVDDQ~2.5V1N4004VDDISPR4096AVSSGNDVSSQNote: The VDDI PIN must work at 2.25V - 2.75V for reliability consideration.

VSUPPLY (working voltage) < 2.75V

VDDQ = VDDI = VSUPPLY, VPP = NC, VSS = VSSQ = GND VSUPPLY(2.5V)VDDQVDDQVDDISPR4096AVSSGNDVSSQ

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7.2. Bus Interface

7.2.1. Cascade access mode (type A, C, G)

To expand memory in SPR4096A, a cascade access mode is designed to identify local memory and expanded memory. It is defined by the configuration control signal, mentioned in the

previous section. For old version of SPL series, it is recommended to expand only to volume 1 (The built-in volume ID is fixed to 1 for Type C and Type G).

ADlocal memoryBFIMEMORYexpanded memoryBFIMEMORYVOLUME 0Type AVOLUME 1Type C, GMC0MC1

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7.2.2. Bus Interface

MC0MC1MC0MC1SPR4096AAD[7:0]AD[7:0]CF[6:3]=0000bCF[6:3]MC0MC1SPR4096AAD[7:0]CF[6:3]=0001bCF[6:3]MC0MC1SPR4096AAD[7:0]CF[6:3]=1111bCF[6:3]

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7.3. Serial Interface

CF[2:0]=111bCF[2:0]CF[4:3]=00bCF[4:3]SPR4096ASCKSDARESETSCKSDARESETCF[2:0]CF[4:3]=01bCF[4:3]SPR4096ASCKSDARESETCF[2:0]CF[4:3]=11bCF[4:3]SPR4096ASCKSDARESET © Sunplus Technology Co., Ltd. Proprietary & Confidential 24 OCT. 01, 2003Version: 1.2

SPR4096A

8. PACKAGE / PAD LOCATIONS

302928272625242322

CF0CF1CF2CF3CF4CF5CF6CF7VDDQ

1VSS2NC3RESET4SCK5VDDQ6VSS7MC08MC19VDDI10111213

VSSQSDAAD0AD1141516171819AD2AD3AD4AD5AD6AD72021VDDQNC

Chip Size : 2790µm × 3330µm

This IC substrate should be connected to VSS

Please contact Sunplus sales representatives for more information. PAD No. PAD Name X Y 1 VSS 113.50 2 NC 233.50 3 RESET 353.50 4 SCK 473.50 5 VDDQ 593.48 6 VSS 713.48 7 MC0 833.48 8 MC1 953.48 9 VDDI 1073.48 10 SDA 1198.48 110.00 11 VSSQ 1318.48 12 AD0 1438.48 13 AD1 1558.48 14 AD2 1678.48 15 AD3 1798.48 16 AD4 1918.48 17 AD5 2038.48 18 AD6 2158.48 19 AD7 2278.48 20 VDDQ 2398.48 21 NC 2574.00 120.00 © Sunplus Technology Co., Ltd. Proprietary & Confidential

OCT. 01, 2003Version: 1.2

SPR4096A

22 VDDQ 23 CF7 24 CF6 25 CF5 2576.50 26 CF4 27 CF3 28 CF2 29 CF1 30 CF0

677.77 945.73 1208.57 1476.53 1739.37 2007.33 2270.17 2538.13 2800.97

8.1 DIP24

PAD Name PIN No. PAD Name PIN No. VDDI 1 NC 13 SDA 2 NC 14 VSSQ 3 NC 15 VDDQ 4 NC 16 CF7 5 NC 17 CF4 6 NC 18 CF3 7 NC 19 CF2~0 8 VSS 20 NC 9 RESET 21 NC 10 SCK 22 NC 11 VDDQ 23 NC 12 VSS 24

8.2 PLCC84

PAD Name PIN No. PAD Name PIN No. VSS 12 AD4 27 NC 13 AD5 28 RESET 14 AD6 29 SCK 15 AD7 30 VDDQ 16 VDDQ 31 VSS 17 NC 32 MC0 18 VDDQ 33 MC1 19 CF7 34 VDDI 20 CF6 35 SDA 21 CF5 36 VSSQ 22 CF4 37 AD0 23 CF3 38 AD1 24 CF2 39 © Sunplus Technology Co., Ltd. Proprietary & Confidential

OCT. 01, 2003Version: 1.2

SPR4096A

AD2 25 CF1 40 AD3 26 CF0 41

其他沒寫的腳位是NC.不接即可.

DISCLAIMER

The information appearing in this publication is believed to be accurate.

Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only.

27 OCT. 01, 2003Version: 1.2

SPR4096A

9. REVISION HISTORY

Date Revision # Description

Page

OCT. 01, 2003 1.2 Add two items: “Endurance: 20,000 Cycles (min)” and “Data Retention: 100 years under Room Temperature” in “2. FEATURES”

MAR. 12, 2003 NOV. 29, 2002 JAN. 29, 2002

1.1 1.0 0.1

Delete “8. PACKAGE/PAD LOCATIONS” Document Release Original

24 - 25

28 OCT. 01, 2003Version: 1.2

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